公开(公告)号：US20150254130A1

公开(公告)日：2015-09-10

申请号：US14200736

申请日：2014-03-07

申请人： Kabushiki Kaisha Toshiba

发明人： Kenji SAKAUE ,  Kouji Saitou ,  Tatsuyuki Ishikawa ,  Kazuhiro Ichikawa ,  Naoaki Kokubun ,  Hironori Uchikawa

IPC分类号： G06F11/10

CPC分类号： H03M13/116 ,  H03M13/1122 ,  H03M13/1137

摘要： According to an embodiment, an error correction decoder includes a first calculation circuit and a second calculation circuit. The first calculation circuit and the second calculation circuit perform the column processing based on the second reliability information corresponding to variable nodes belonging to each of one or more valid blocks arranged in a first row group and the row processing based on the first reliability information corresponding to variable nodes belonging to one or more valid blocks arranged in a second row group whose processing order is later than that of the first row group in parallel.

摘要翻译： 根据实施例，纠错解码器包括第一计算电路和第二计算电路。 第一计算电路和第二计算电路基于与属于第一行组中布置的一个或多个有效块中的每一个的可变节点相对应的第二可靠性信息执行列处理，并且基于与第一计算电路相对应的第一可靠性信息的行处理 属于一个或多个有效块的可变节点，其排列在第二行组中，其处理顺序比第一行组的处理顺序晚。

公开(公告)号：US20140068379A1

公开(公告)日：2014-03-06

申请号：US13803803

申请日：2013-03-14

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kenji SAKAUE

IPC分类号： G06F11/10

CPC分类号： G06F11/10 ,  G06F11/1012

摘要： According to one embodiment, a memory module which includes a plurality of nonvolatile memory cells with a plurality of pages and line-and-space word lines to which more than one of the memory cells are connected, and a controller which receives write data from a host device.

摘要翻译： 根据一个实施例，一种存储器模块，其包括具有多个页面的多个非易失性存储器单元和连接多于一个存储器单元的行和空格字线以及从一个存储单元接收写入数据的控制器 主机设备。

公开(公告)号：US20160020787A1

公开(公告)日：2016-01-21

申请号：US14531039

申请日：2014-11-03

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuyuki ISHIKAWA ,  Kazuhiro ICHIKAWA ,  Toshihiko KITAZUME ,  Kenji SAKAUE ,  Kouji SAITOU

IPC分类号： H03M13/11

CPC分类号： H03M13/114 ,  H03M13/1137

摘要： According to one embodiment, a parallel processor performs the row processes in parallel in a LDPC decode while performing the column processes in parallel in the LDPC decode, and a control circuit alternately repeats the parallel processes of the row process and the parallel processes of the column process as many times as the number of rows and columns in a check matrix and divides the parallel rows for the row process when the LDPC decode is started.

摘要翻译： 根据一个实施例，并行处理器在LDPC解码中并行地执行LDPC解码并行执行行处理，并且控制电路交替地重复行处理和列的并行处理的并行处理 处理与校验矩阵中的行和列数相同的次数，并且当LDPC解码开始时对行处理的并行进行划分。

公开(公告)号：US20150058705A1

公开(公告)日：2015-02-26

申请号：US14093190

申请日：2013-11-29

申请人： Kabushiki Kaisha Toshiba

发明人： Kenji SAKAUE ,  Edward Bandy SAMIGAT ,  Atsushi TAKAYAMA ,  Yutaka TANGO

IPC分类号： G11C16/32 ,  H03M13/09

CPC分类号： G11C16/32 ,  G06F13/1689 ,  G11C7/106 ,  G11C7/1066 ,  H03M13/09 ,  H03M13/1515 ,  H03M13/152

摘要： According to one embodiment, a storage device includes a storage medium, a DLL circuit, a latch circuit, and a delay amount adjustment circuit. The DLL circuit gives a predetermined amount of delay to an inputted clock signal, the latch circuit latches data outputted from the storage medium in accordance with the clock signal delayed in the DLL circuit, the delay amount adjustment circuit adjusts the delay amount that the DLL circuit is to give to the clock signal based on a latch result by the latch circuit.

摘要翻译： 根据一个实施例，存储装置包括存储介质，DLL电路，锁存电路和延迟量调整电路。 DLL电路对输入的时钟信号给出预定量的延迟时间，锁存电路根据在DLL电路中延迟的时钟信号来锁存从存储介质输出的数据，延迟量调整电路调整DLL电路的延迟量 是基于锁存电路的锁存结果给予时钟信号。

公开(公告)号：US20140298142A1

公开(公告)日：2014-10-02

申请号：US14303280

申请日：2014-06-12

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kenji SAKAUE ,  Atsushi TAKAYAMA ,  Yoshihisa KONDO ,  Tatsuyuki ISHIKAWA

IPC分类号： G06F11/10

CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G11C29/00 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/1177 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/45 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/6577

摘要： A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.

摘要翻译： 一种存储器控制器，包括：缓冲器，被配置为基于由单位矩阵的块和多个块组成的校验矩阵，通过部分并行处理来执行由LDPC解码器解码的帧单元数据，其中，每行单位矩阵 顺序地移位并存储从存储器部分读取的数据的阈值判定信息，被配置为将阈值判定信息转换为LLR的LLR转换部分，被配置为存储概率信息＆lt; bgr的LMEM; 在迭代处理期间计算的重复执行列处理和基于等于或小于块的大小的迭代单元中的LLR的行处理以及被配置为传送概率信息＆bgr的CPU核心; 每次迭代单元中的迭代处理完成时，将LMEM存储在缓冲区中。

公开(公告)号：US20140281794A1

公开(公告)日：2014-09-18

申请号：US13963125

申请日：2013-08-09

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kenji SAKAUE

IPC分类号： G06F11/10

CPC分类号： G06F11/1012

摘要： According to one embodiment, an error correction circuit includes a first memory module, a read-out module, a first arithmetic module, a detector, a second arithmetic module, and a transfer module. The first memory module stores logarithmic likelihood ratio (LLR) data to which low density parity check codes (LDPC) data has been converted. The read-out module reads out, from the first memory module, the LLR data of a plurality of variable nodes which are connected to a selected check node, based on a check matrix. The first and second arithmetic modules update the LLR data, based on the read-out LLR data and first and second reliability data. The transfer module transfers the updated LLR data to the first memory module.

摘要翻译： 根据一个实施例，纠错电路包括第一存储器模块，读出模块，第一算术模块，检测器，第二算术模块和传输模块。 第一存储器模块存储已经转换低密度奇偶校验码（LDPC）数据的对数似然比（LLR）数据。 读出模块基于校验矩阵从第一存储器模块读出连接到所选校验节点的多个变量节点的LLR数据。 第一和第二算术模块基于读出的LLR数据和第一和第二可靠性数据更新LLR数据。 传输模块将更新的LLR数据传送到第一存储器模块。