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公开(公告)号:US20140027858A1
公开(公告)日:2014-01-30
申请号:US14047720
申请日:2013-10-07
发明人: Mitsuhiko KITAGAWA
IPC分类号: H01L27/088
CPC分类号: H01L27/088 , H01L29/0634 , H01L29/0856 , H01L29/0878 , H01L29/4236 , H01L29/7391 , H01L29/7394 , H01L29/7397 , H01L29/7813 , H01L29/7824 , H01L29/7825 , H01L29/7828 , H01L29/7831 , H01L29/7838
摘要: A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.
摘要翻译: 半导体器件包括:具有第一端部和第二端部的半导体层; 第一主电极,设置在第一端部上并与半导体层电连接; 第二主电极,设置在第二端部并与半导体层电连接; 第一栅电极,其经由第一栅极绝缘膜设置在由所述第一端部朝向所述第二端部形成的多个第一沟槽中; 以及第二栅电极,其经由第二栅极绝缘膜设置在由所述第二端部朝向所述第一端部形成的多个第二沟槽中。 多个第一栅电极之间的间隔和多个第二栅电极之间的间隔为200nm以下。
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公开(公告)号:US20130248886A1
公开(公告)日:2013-09-26
申请号:US13754602
申请日:2013-01-30
发明人: Mitsuhiko KITAGAWA
IPC分类号: H01L29/06
CPC分类号: H01L29/0646 , H01L25/112 , H01L25/115 , H01L25/117 , H01L25/162 , H01L29/0615 , H01L29/0661 , H01L29/0834 , H01L29/7397 , H01L2924/0002 , H01L2924/00
摘要: In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, and including a first semiconductor layer of a first conductivity type in the substrate, a second semiconductor layer of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, a third semiconductor layer of the first conductivity type on a surface of the second semiconductor layer, and a fourth semiconductor layer of the second conductivity type on a surface of the first semiconductor layer on a second main surface side. The device further includes a control electrode and a first main electrode on the first main surface side of the substrate, and a second main electrode and a junction termination portion on the second main surface side of the substrate, the junction termination portion having an annular planar shape surrounding the fourth semiconductor layer.
摘要翻译: 在一个实施例中,半导体器件包括具有第一和第二主表面的半导体衬底,并且在衬底中包括第一导电类型的第一半导体层,在第一半导体层的表面上具有第二导电类型的第二半导体层 在第一主表面侧,在第二主表面侧的第一半导体层的表面上,在第二半导体层的表面上具有第一导电类型的第三半导体层和第二导电类型的第四半导体层。 该装置还包括在基板的第一主表面侧上的控制电极和第一主电极,以及在基板的第二主表面侧上的第二主电极和接合端接部分,连接端接部分具有环形平面 围绕第四半导体层的形状。
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公开(公告)号:US20150001668A1
公开(公告)日:2015-01-01
申请号:US14487975
申请日:2014-09-16
发明人: Mitsuhiko KITAGAWA
CPC分类号: H01L29/0634 , H01L27/0629 , H01L27/0814 , H01L29/063 , H01L29/0638 , H01L29/1608 , H01L29/2003 , H01L29/205 , H01L29/41 , H01L29/7803 , H01L29/7804 , H01L29/7805 , H01L29/7813 , H01L29/861 , H01L29/8611
摘要: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.
摘要翻译: 根据一个实施例,提供一种半导体器件。 半导体器件具有由半导体形成的第一区域和与半导体形成的与第一区域接合的第二区域。 电极形成为与第一区域欧姆连接。 形成第三区域以夹持第一区域。 根据第三区域和第一区域之间的第二电位差,在热平衡状态下的第一和第二区域之间产生第一电位差。
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公开(公告)号:US20230090328A1
公开(公告)日:2023-03-23
申请号:US17689850
申请日:2022-03-08
IPC分类号: H01L27/06 , H01L29/10 , H01L29/861 , H01L29/739
摘要: A semiconductor device includes: a first semiconductor layer located in a diode region, the first semiconductor layer including a plurality of first semiconductor regions and a plurality of second semiconductor regions alternately arranged in a first direction; a second semiconductor layer located in the IGBT region; and a third semiconductor layer located on the first semiconductor layer in the diode region, an impurity concentration of the third semiconductor layer having a maximum at a first position in a second direction, an impurity concentration of the first semiconductor region having a maximum at a second position in the second direction, a third position being separated from the upper surface of the first electrode by a length that is 3 times a distance between the second position and a lower end of the third semiconductor layer, the first position being the same as or lower than the third position.
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公开(公告)号:US20170133456A1
公开(公告)日:2017-05-11
申请号:US15416215
申请日:2017-01-26
发明人: Mitsuhiko KITAGAWA
IPC分类号: H01L29/06 , H01L29/78 , H01L29/861 , H01L29/16 , H01L29/20 , H01L29/205
CPC分类号: H01L29/0634 , H01L27/0629 , H01L27/0814 , H01L29/063 , H01L29/0638 , H01L29/1608 , H01L29/2003 , H01L29/205 , H01L29/41 , H01L29/7803 , H01L29/7804 , H01L29/7805 , H01L29/7813 , H01L29/861 , H01L29/8611
摘要: According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed of semiconductor which borders the first region. An electrode is formed to be in ohmic-connection with the first region. A third region is formed to sandwich the first region. A first potential difference is produced between the first and the second regions in a thermal equilibrium state, according to a second potential difference between the third region and the first region.
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公开(公告)号:US20180083129A1
公开(公告)日:2018-03-22
申请号:US15446642
申请日:2017-03-01
发明人: Mitsuhiko KITAGAWA
IPC分类号: H01L29/739 , H01L29/10 , H01L29/08 , H01L29/36
CPC分类号: H01L29/7395 , H01L21/743 , H01L29/0696 , H01L29/0804 , H01L29/0821 , H01L29/083 , H01L29/1004 , H01L29/1095 , H01L29/36 , H01L29/407 , H01L29/66181 , H01L29/7397 , H01L29/7813 , H01L29/945
摘要: A semiconductor device includes a first electrode, a first semiconductor region disposed on and electrically connected to the first electrode, a second semiconductor region disposed on the first semiconductor region and having a carrier concentration lower than that of the first semiconductor region, a third semiconductor region disposed on the second semiconductor region, a fourth semiconductor region disposed on the third semiconductor region, a fifth semiconductor region disposed on the second semiconductor region and separated from the third semiconductor region in a direction, a gate electrode disposed on the second semiconductor region, facing the third semiconductor region via an insulating layer in the direction and positioned between the third and fourth semiconductor regions, a second electrode disposed on and electrically connected to the fourth semiconductor region, and a third electrode disposed on the fifth semiconductor region, separated from the second electrode, and electrically connected to the fifth semiconductor region.
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公开(公告)号:US20140191282A1
公开(公告)日:2014-07-10
申请号:US14207200
申请日:2014-03-12
发明人: Mitsuhiko KITAGAWA
IPC分类号: H01L27/06
CPC分类号: H01L27/0664 , H01L29/1608 , H01L29/2003 , H01L29/7397 , H01L29/861 , H01L29/868
摘要: According to one embodiment, a semiconductor device includes a base layer, a second conductivity type semiconductor layer, a first insulating film, and a first electrode. The first insulating film is provided on an inner wall of a plurality of first trenches extending from a surface of the second conductivity type semiconductor layer toward the base layer side, but not reaching the base layer. The first electrode is provided in the first trench via the first insulating film, and provided in contact with a surface of the second conductivity type semiconductor layer. The second conductivity type semiconductor layer includes a first second conductivity type region, and a second second conductivity type region. The first second conductivity type region is provided between the first trenches. The second second conductivity type region is provided between the first second conductivity type region and the base layer, and between a bottom part of the first trench and the base layer. The second second conductivity type region is smaller in a quantity of second conductivity type impurities than the first second conductivity type region.
摘要翻译: 根据一个实施例,半导体器件包括基极层,第二导电型半导体层,第一绝缘膜和第一电极。 第一绝缘膜设置在从第二导电类型半导体层的表面朝向基底层侧延伸但不到达基底层的多个第一沟槽的内壁上。 第一电极经由第一绝缘膜设置在第一沟槽中,并与第二导电型半导体层的表面接触。 第二导电型半导体层包括第一第二导电类型区域和第二第二导电类型区域。 第一第二导电类型区域设置在第一沟槽之间。 第二第二导电类型区域设置在第一第二导电类型区域和基底层之间以及第一沟槽的底部与基底层之间。 第二第二导电类型区域的第二导电类型杂质的量比第一第二导电类型区域小。
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