公开(公告)号：US20250098298A1

公开(公告)日：2025-03-20

申请号：US18591188

申请日：2024-02-29

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tomoaki INOKUCHI ,  Hiro GANGI ,  Yusuke KOBAYASHI ,  Tatsunori SAKANO ,  Tatsuo SHIMIZU ,  Shotaro BABA ,  Taichi FUKUDA

IPC: H01L27/12 ,  H01L27/02 ,  H01L29/40 ,  H01L29/47 ,  H01L29/812

Abstract: The major element includes a first electrode, a second electrode, a first semiconductor layer located between the first electrode and the second electrode, the first semiconductor layer forming a first Schottky junction with the second electrode, and a first gate electrode facing the first Schottky junction. The control element includes a third electrode, a fourth electrode, a second semiconductor layer located between the third electrode and the fourth electrode, the second semiconductor layer forming a second Schottky junction with the fourth electrode, and a second gate electrode facing the second Schottky junction.

公开(公告)号：US20220293754A1

公开(公告)日：2022-09-15

申请号：US17399278

申请日：2021-08-11

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Tomoaki INOKUCHI ,  Hiro GANGI ,  Yusuke KOBAYASHI ,  Hiroki NEMOTO

IPC: H01L29/423 ,  H01L29/47 ,  H01L29/78

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a first conductive member, and an insulating part region. The second electrode includes a first electrode portion. The semiconductor member includes a first semiconductor region. The first semiconductor region includes first to third partial regions. The first partial region is between the first electrode and the first electrode portion. The second partial region is between the first and third electrodes. The third partial region is between the first partial region and the first electrode portion. The third partial region includes first and second positions. The second position is between the first partial region and the first position. The first conductive member includes first and second portions. The first portion is between the second partial region and the third electrode. The insulating part region includes first and second insulating regions.

公开(公告)号：US20220140133A1

公开(公告)日：2022-05-05

申请号：US17395910

申请日：2021-08-06

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiro GANGI ,  Yasunori TAGUCHI ,  Tomoaki INOKUCHI ,  Yusuke KOBAYASHI ,  Hiroki NEMOTO

IPC: H01L29/78 ,  H01L29/40

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a conductive member, and an insulating member. The semiconductor member includes first to third semiconductor regions. The first semiconductor region includes first and second partial regions. The second semiconductor region is between the first partial region and the third semiconductor region. The conductive member is located between the second partial region and the third electrode. The conductive member includes a first end portion and a first other-end portion. The first end portion is between the first other-end portion and the third electrode. The conductive member includes first to third portions. The second portion is between the third portion and the third electrode. The first portion is between the second portion and the third electrode. The first portion includes the first end portion. The second portion contacts the first and third portions.

公开(公告)号：US20210328027A1

公开(公告)日：2021-10-21

申请号：US17155193

申请日：2021-01-22

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiro GANGI ,  Yusuke KOBAYASHI ,  Tomoaki INOKUCHI ,  Tatsunori SAKANO

IPC: H01L29/40 ,  H01L29/78

Abstract: According to one embodiment, a semiconductor device includes first, second, third semiconductor members, a first conductive member, a connection member, and an insulating member. The first electrode includes first, second, and third electrode regions. A direction from the first toward second electrode is along a first direction. The second electrode includes fourth, fifth, and sixth electrode regions. The first semiconductor member includes first, second, third, fourth, and fifth partial regions. The second semiconductor member includes first and second semiconductor regions. The third semiconductor member includes third and fourth semiconductor regions. The third electrode is provided between the third partial region and the sixth electrode region in the first direction. The connection member is electrically connected to the first conductive member and the second electrode. The insulating member includes first, second, third, fourth, and fifth portions. The fifth portion contacts the first semiconductor region and the connection member.

公开(公告)号：US20210242341A1

公开(公告)日：2021-08-05

申请号：US17015406

申请日：2020-09-09

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

Inventor： Yusuke KOBAYASHI ,  Hiro GANGI ,  Tomoaki INOKUCHI ,  Ryohei GEJO

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L21/765 ,  H01L29/66

Abstract: According to one embodiment, a semiconductor device includes first, second, and third electrodes, first, second, and third semiconductor regions, a first member, and a first insulating member. A direction from the first electrode toward the second electrode is along a first direction. The first semiconductor region includes first, second, and third partial regions. A second direction from the second partial region toward the first partial region crosses the first direction. The third partial region is between the second partial region and the second semiconductor region in the first direction. The third semiconductor region is provided between the third partial region and the second semiconductor region. The first insulating member includes a first insulating region and a second insulating region. The first insulating region is between the third partial region and the first member. The second insulating region is between the third semiconductor region and the third electrode.

公开(公告)号：US20170104032A1

公开(公告)日：2017-04-13

申请号：US15384501

申请日：2016-12-20

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yusuke KOBAYASHI ,  Yoshihisa IWATA ,  Takeshi SUGIMOTO

IPC: H01L27/24 ,  H01L23/528

CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L27/2436

Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.

公开(公告)号：US20170069688A1

公开(公告)日：2017-03-09

申请号：US15068019

申请日：2016-03-11

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yusuke KOBAYASHI

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/1675

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer separated from the first conductive layer in a first direction, a resistance change layer provided between the first and second conductive layers, a third conductive layer, a fourth conductive layer and a first intermediate layer. The third conductive layer is arranged with the first conductive layer in a second direction crossing the first direction. The fourth conductive layer is arranged with the second conductive layer in a direction crossing the first direction. The fourth conductive layer is arranged with the third conductive layer in the first direction. The fourth conductive layer is electrically connected with the third conductive layer. The first intermediate layer is provided between a portion of the third conductive layer and a portion of the fourth conductive layer.

Abstract translation: 根据一个实施例，半导体存储器件包括第一导电层，在第一方向与第一导电层分离的第二导电层，设置在第一和第二导电层之间的电阻变化层，第三导电层，第四导电层 导电层和第一中间层。 第三导电层被布置成与第一方向交叉的第二方向上具有第一导电层。 第四导电层与第二导电层沿与第一方向交叉的方向布置。 第四导电层沿第一方向布置有第三导电层。 第四导电层与第三导电层电连接。 第一中间层设置在第三导电层的一部分和第四导电层的一部分之间。

公开(公告)号：US20250169124A1

公开(公告)日：2025-05-22

申请号：US18735309

申请日：2024-06-06

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

Inventor： Hiro GANGI ,  Tomoaki INOKUCHI ,  Yusuke KOBAYASHI ,  Shotaro BABA ,  Hiroki NEMOTO ,  Taichi FUKUDA

IPC: H01L29/06 ,  H01L23/528 ,  H01L29/26 ,  H01L29/47

Abstract: A semiconductor device includes a support body, a first conductive part, a second conductive part, a semiconductor layer, a third conductive part, and a fourth conductive part. The semiconductor layer includes a first end surface, a second end surface, a counter region, and a first semiconductor region. The first semiconductor region is of a first conductivity type. The first semiconductor region includes a first upper end region, a first lower end region, and a first intermediate region. The first upper end region includes a portion of the first end surface. The first lower end region includes a portion of the second end surface. A first-conductivity-type impurity concentration in the first upper end region is greater than a first-conductivity-type impurity concentration in the first intermediate region. A first-conductivity-type impurity concentration in the first lower end region is greater than the first-conductivity-type impurity concentration in the first intermediate region.

公开(公告)号：US20240054272A1

公开(公告)日：2024-02-15

申请号：US18174937

申请日：2023-02-27

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hiro GANGI ,  Yasunori TAGUCHI ,  Hideyuki NAKAGAWA ,  Tomoaki INOKUCHI ,  Yusuke KOBAYASHI ,  Akihiro GORYU

IPC: G06F30/367

CPC classification number: G06F30/367 ,  G06F2111/10

Abstract: An information processing apparatus according to one embodiment, comprising: a regression model generator configured to, by combining two or more of a plurality of variables, generate a plurality of terms that include combinations of two or more of the plurality of variables, respectively, and generate a regression model that regresses a property variable or an objective variable indicating an output of an objective function that includes the property variable, by the plurality of terms; a subgroup generator configured to generate, based on coefficients of the plurality of terms included in the regression model, subgroups that are the combinations of variables included the terms, respectively; and a subspace search processor configured to perform search for each of subspaces spanned by the subgroups based on an optimization criterion for the objective function, and generate pieces of first design value data that include values of the plurality of variables for the subspaces.

公开(公告)号：US20230253485A1

公开(公告)日：2023-08-10

申请号：US17816827

申请日：2022-08-02

Applicant: KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION

Inventor： Takahiro KATO ,  Tatsunori SAKANO ,  Yusuke KOBAYASHI ,  Ryohei GEJO

IPC: H01L29/739 ,  H01L29/10 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7397 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/0696 ,  H01L29/4238

Abstract: According to one embodiment, a semiconductor device includes first to fourth electrodes, a semiconductor member, and an insulating member. The semiconductor member includes first to sixth semiconductor regions. The third semiconductor region includes first and second partial regions. A part of the fourth semiconductor region is between the second partial and second semiconductor regions. The fifth semiconductor region is between the second partial region and a part of the fourth semiconductor region. The sixth semiconductor region is between the first electrode and the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The fourth electrode is between the first partial region and the third electrode. A part of the insulating member is provided between the semiconductor member and the third electrode, between the semiconductor member and the fourth electrode, and between the third and fourth electrodes.