公开(公告)号：US20160077555A1

公开(公告)日：2016-03-17

申请号：US14844511

申请日：2015-09-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yuuta YAMADA ,  Takeshi MITSUHASHI ,  Junichi ASADA

IPC: G06F1/18 ,  G11C16/04

CPC classification number: G06K19/07732 ,  H05K5/0278

Abstract: According to one embodiment, a USB memory device includes: a substrate including a semiconductor chip, a plurality of operating terminals, a reference potential terminal and a reference potential wiring; and a housing holding the substrate inside, being electrically connected to the reference potential terminal, and having electric conductivity. The reference potential wiring electrically connects the operating terminal with the reference potential terminal.

Abstract translation: 根据一个实施例，USB存储器件包括：衬底，其包括半导体芯片，多个操作终端，参考电位端子和参考电位布线; 以及将基板保持在内部的壳体，其电连接到基准电位端子并具有导电性。 参考电位布线将操作端子与参考电位端子电连接。

公开(公告)号：US20150043228A1

公开(公告)日：2015-02-12

申请号：US14151192

申请日：2014-01-09

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Hideyuki KOGURE ,  Yuuta YAMADA ,  Takeshi IKUTA ,  Toshiyuki HAYAKAWA ,  Junichi ASADA

IPC: F21K99/00 ,  H05K1/18 ,  H01L21/78

CPC classification number: F21K9/30 ,  F21K9/20 ,  F21Y2115/10 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3135 ,  H01L24/73 ,  H01L24/97 ,  H01L25/167 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15151 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/186 ,  H05K2201/10106 ,  H05K2201/10159 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85

Abstract: According to one embodiment, a semiconductor device includes a board, a controller chip, a semiconductor chip, a sealing portion, and a component. The board includes a first surface and a second surface opposite to the first surface, the first surface comprising a terminal. The controller chip is on the second surface of the board. The semiconductor chip is on the second surface of the board. The sealing portion integrally covers the controller chip and the semiconductor chip and does not cover a region of the second surface of the board. The component is on the region of the second surface of the board to perform an operation with respect to the outside of the semiconductor device.

Abstract translation: 根据一个实施例，半导体器件包括板，控制器芯片，半导体芯片，密封部分和部件。 板包括与第一表面相对的第一表面和第二表面，第一表面包括端子。 控制器芯片位于电路板的第二个表面上。 半导体芯片位于板的第二表面上。 密封部一体地覆盖控制器芯片和半导体芯片，并且不覆盖板的第二表面的区域。 该部件位于板的第二表面的区域上，以对半导体器件的外部进行操作。

公开(公告)号：US20160118753A1

公开(公告)日：2016-04-28

申请号：US14844409

申请日：2015-09-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takeshi IKUTA ,  Yuuta YAMADA

IPC: H01R13/66 ,  H01R13/52

CPC classification number: H05K5/0278

Abstract: According to one embodiment, a semiconductor memory device includes: a substrate including a memory capable of storing data and a controller controlling the memory, and a housing including first and second housing parts and holding the substrate therein. The first housing part includes a fixing unit which has elasticity and is in contact with the substrate.

Abstract translation: 根据一个实施例，半导体存储器件包括：衬底，其包括能够存储数据的存储器和控制存储器的控制器;以及壳体，其包括第一和第二壳体部分并将衬底保持在其中。 第一壳体部分包括具有弹性并与基底接触的固定单元。

公开(公告)号：US20140287605A1

公开(公告)日：2014-09-25

申请号：US14142098

申请日：2013-12-27

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yuuta YAMADA ,  Junichi Asada

IPC: H01R13/44

CPC classification number: H01R13/447

Abstract: According to one embodiment, a semiconductor device includes a case, a connector, and a cap. The case includes a first main surface, a second main surface opposite to the first main surface, a first concave portion provided with at least one of the first main surface and the second main surface, and a semiconductor memory housed inside. The connector is connected to the case. The cap includes a third main surface, a fourth main surface opposite to the third main surface, a locking portion provided with at least one of the third main surface and the fourth main surface which is locked with the first concave portion, and a side surface provided with an opening portion opening between the third main surface and the fourth main surface.

Abstract translation: 根据一个实施例，半导体器件包括壳体，连接器和盖。 壳体包括第一主表面，与第一主表面相对的第二主表面，设置有第一主表面和第二主表面中的至少一个的第一凹部和容纳在内部的半导体存储器。 连接器连接到外壳。 盖包括第三主表面，与第三主表面相对的第四主表面，设置有与第一凹部锁定的第三主表面和第四主表面中的至少一个的锁定部分，以及侧表面 在所述第三主表面和所述第四主表面之间设置有开口部分开口。