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公开(公告)号：US20240324227A1
公开(公告)日：2024-09-26
申请号：US18593379
申请日：2024-03-01
Applicant: Kioxia Corporation
Inventor： Hiroyuki YAMASHITA , Tatsunori ISOGAI , Masaki NOGUCHI , Junichi KANEYAMA , Shin ISHIMATSU , Daisuke NISHIDA , Tomoyuki TAKEMOTO , Wataru MATSUURA
Abstract: A semiconductor device includes a stack including a conductor layer and an insulator layer, a block insulating layer, a channel layer, a charge storage layer provided between the block insulating layer and the channel layer, and a tunnel layer provided between the charge storage layer and the channel layer, where the charge storage layer includes a first charge storage layer containing Si, N and at least one of Al, Mo, Nb, Hf, Zr, Ti, B, or P, a second charge storage layer containing Si and N, in which Si is contained at a second concentration higher than a first concentration that is a concentration of Si in the first charge storage layer, and provided between the first charge storage layer and the tunnel layer, and a dielectric layer containing at least one of silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or aluminum oxide (AlOx), and provided between the first charge storage layer and the second charge storage layer.
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公开(公告)号：US20220084799A1
公开(公告)日：2022-03-17
申请号：US17466285
申请日：2021-09-03
Applicant: Kioxia Corporation
Inventor： Motoki FUJII , Daisuke NISHIDA
Abstract: A semiconductor manufacturing apparatus according to an embodiment includes: a chamber that houses a semiconductor substrate; and a plurality of coils provided on a lateral surface of the chamber. The chamber has a first spatial region enclosed above the semiconductor substrate by a first coil that is one of the plurality of coils, a first gas introduction port communicating with the first spatial region, a second spatial region enclosed by a second coil that is different from the first coil among the plurality of coils, and a second gas introduction port communicating with the second spatial region.
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公开(公告)号：US20240315036A1
公开(公告)日：2024-09-19
申请号：US18593502
申请日：2024-03-01
Applicant: Kioxia Corporation
Inventor： Shin ISHIMATSU , Tatsunori ISOGAI , Masaki NOGUCHI , Hiroyuki YAMASHITA , Wataru MATSUURA , Daisuke NISHIDA , Junichi KANEYAMA , Tomoyuki TAKEMOTO
CPC classification number: H10B43/35 , G11C16/0483 , H10B41/27 , H10B41/35 , H10B43/27
Abstract: According to one embodiment, a semiconductor memory device includes a stacked film in which a plurality of silicon oxide layers, one of which having a film density of 2.3 g/cm3 or more, and a plurality of conductive layers, are alternately stacked in a first direction, and a memory pillar that penetrates the stacked film in the first direction, wherein a plurality of memory cells is provided in the memory pillar.
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公开(公告)号：US20230292506A1
公开(公告)日：2023-09-14
申请号：US17898148
申请日：2022-08-29
Applicant: KIOXIA CORPORATION
Inventor： Daisuke NISHIDA
IPC: H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L23/528
CPC classification number: H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L23/5283
Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers and a plurality of insulating layers, the electrode layers and the insulating layers being alternately stacked, and a memory film extending in a stacking direction in the stacked body. The memory film includes an oxide film facing the insulating layers, a block insulating film facing the electrode layers and the oxide film, and a charge storage film facing the block insulating film. The block insulating film has a larger thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers, and the charge storage film has a smaller thickness at a portion facing each of the insulating layers than at a portion facing each of the electrode layers.
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