公开(公告)号：US20210327515A1

公开(公告)日：2021-10-21

申请号：US17363005

申请日：2021-06-30

Applicant: KIOXIA CORPORATION

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  H01L27/11582 ,  H01L27/11565 ,  G11C16/08

Abstract: A semiconductor memory device includes a controller which executes a read operation. In the read operation, the controller applies first and second read voltages to a word line, reads data at each of first and second times, applies the first voltage to a source line at each of the first and second times, applies a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and applies a third voltage to the source line during the application of the second read voltage to the word line and before the second time.

公开(公告)号：US20250069670A1

公开(公告)日：2025-02-27

申请号：US18946968

申请日：2024-11-14

Applicant: Kioxia Corporation

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32 ,  H10B43/10 ,  H10B43/27

Abstract: A memory system includes a semiconductor memory device and a memory controller configured to send a command to the device. The device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a sequencer. The sequencer, in response to the command, reads data stored by the memory cell by applying a first voltage to the first transistor and a second voltage to the source line during a first time period, applying a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applying the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.

公开(公告)号：US20230119989A1

公开(公告)日：2023-04-20

申请号：US18084363

申请日：2022-12-19

Applicant: Kioxia Corporation

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  H10B43/27 ,  H10B43/10 ,  G11C16/08

Abstract: A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.

公开(公告)号：US20210335418A1

公开(公告)日：2021-10-28

申请号：US17198375

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI ,  Takeshi HIOKA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

公开(公告)号：US20230377662A1

公开(公告)日：2023-11-23

申请号：US18228166

申请日：2023-07-31

Applicant: Kioxia Corporation

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/08 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor memory device includes a memory cell connected between a bit line and a source line, a sense amplifier having a first transistor provided between at least two transistors of the sense amplifier and the bit line, and a controller which executes a read operation to read data stored by the memory cell. In the read operation, the controller applies a first voltage to the first transistor and a second voltage to the source line during a first time period, applies a third voltage to the first transistor and a fourth voltage to the source line during a second time period after the first time period, and applies the first voltage to the first transistor and a fifth voltage to the source line during a third time period after the second time period.

公开(公告)号：US20230062330A1

公开(公告)日：2023-03-02

申请号：US18054746

申请日：2022-11-11

Applicant: Kioxia Corporation

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI ,  Takeshi HIOKA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

公开(公告)号：US20210012841A1

公开(公告)日：2021-01-14

申请号：US16774630

申请日：2020-01-28

Applicant: KIOXIA CORPORATION

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11582 ,  H01L27/11565 ,  G11C16/32

Abstract: According to one embodiment, a semiconductor memory device includes a controller configured to execute a read operation. In the read operation, the controller is configured to: apply first and second read voltages to a word line, read data at each of first and second times, apply the first voltage to the source line at each of the first and second times, apply a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and apply a third voltage to the source line during the application of the second read voltage to the word line and before the second time.