SEMICONDUCTOR MEMORY DEVICE
    1.
    发明公开

    公开(公告)号:US20240071478A1

    公开(公告)日:2024-02-29

    申请号:US18504018

    申请日:2023-11-07

    CPC classification number: G11C11/4096 G11C5/063 G11C11/4072 G11C11/4076

    Abstract: A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.

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