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公开(公告)号：US20250022512A1
公开(公告)日：2025-01-16
申请号：US18899645
申请日：2024-09-27
Applicant: Kioxia Corporation
Inventor： Tomoki NAKAGAWA , Koji KATO , Shuhei OKETA , Mai SHIMIZU
Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.
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公开(公告)号：US20240071478A1
公开(公告)日：2024-02-29
申请号：US18504018
申请日：2023-11-07
Applicant: Kioxia Corporation
Inventor： Hideyuki KATAOKA , Yoshinao SUZUKI , Mai SHIMIZU , Kazuyoshi MURAOKA , Masami MASUDA , Yoshikazu HOSOMURA
IPC: G11C11/4096 , G11C5/06 , G11C11/4072 , G11C11/4076
CPC classification number: G11C11/4096 , G11C5/063 , G11C11/4072 , G11C11/4076
Abstract: A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.
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Patent Agency Ranking
公开(公告)号：US20230083392A1
公开(公告)日：2023-03-16
申请号：US17680144
申请日：2022-02-24
Applicant: KIOXIA CORPORATION
Inventor： Yoshikazu HOSOMURA , Hideyuki KATAOKA , Yoshinao SUZUKI , Mai SHIMIZU , Kazuyoshi MURAOKA , Masami MASUDA
IPC: H01L27/11524 , G11C16/04 , G11C5/06 , H01L27/11519 , H01L27/11551 , H01L27/11565 , H01L27/1157 , H01L27/11578
Abstract: A semiconductor storage device includes a memory cell array having a plurality of first conductive layers stacked in a first direction and a plurality of memory cells connected to the plurality of first conductive layers, a wiring layer, and an insulating layer between the memory cell array and the wiring layer and separating the memory cell array and the wiring layer in a second direction intersecting the first direction. The wiring layer includes a plurality of second conductive layers stacked in the first direction, each of the second conductive layers having a corresponding first conductive layer at a same layer, and a contact connected to at least a part of the plurality of second conductive layers and extending in the first direction.
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公开(公告)号：US20240038305A1
公开(公告)日：2024-02-01
申请号：US18485630
申请日：2023-10-12
Applicant: Kioxia Corporation
Inventor： Mai SHIMIZU , Koji KATO , Yoshihiko KAMATA , Mario SAKO
CPC classification number: G11C16/08 , G11C16/30 , G11C16/26 , G11C16/0483 , G11C11/5642 , G11C16/24 , G11C16/32 , G11C16/3427
Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
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公开(公告)号：US20230178152A1
公开(公告)日：2023-06-08
申请号：US18161274
申请日：2023-01-30
Applicant: Kioxia Corporation
Inventor： Mai SHIMIZU , Koji KATO , Yoshihiko KAMATA , Mario SAKO
CPC classification number: G11C16/08 , G11C11/5642 , G11C16/24 , G11C16/26 , G11C16/30 , G11C16/32 , G11C16/0483 , G11C16/3427
Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
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公开(公告)号：US20240420765A1
公开(公告)日：2024-12-19
申请号：US18818527
申请日：2024-08-28
Applicant: Kioxia Corporation
Inventor： Mai SHIMIZU , Koji KATO , Yoshihiko KAMATA , Mario SAKO
Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
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公开(公告)号：US20230307051A1
公开(公告)日：2023-09-28
申请号：US17897089
申请日：2022-08-26
Applicant: KIOXIA CORPORATION
Inventor： Tomoki NAKAGAWA , Koji KATO , Shuhei OKETA , Mai SHIMIZU
CPC classification number: G11C16/08 , G11C16/0483
Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.
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