公开(公告)号：US20230197160A1

公开(公告)日：2023-06-22

申请号：US17898868

申请日：2022-08-30

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Koji KOHARA ,  Keisuke NAKATSUKA

IPC: G11C16/10

CPC classification number: G11C16/10

Abstract: A data latch circuit includes a first transistor of a first conductivity type and a second transistor of the first conductivity type, and a third transistor of a second conductivity type and a fourth transistor of the second conductivity type. The third and fourth transistors are controlled to perform a first control operation to store data in the data latch circuit and to perform a second control operation to read the stored data.

公开(公告)号：US20230178556A1

公开(公告)日：2023-06-08

申请号：US17939874

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Muneaki MAENO ,  Koji KOHARA

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11866 ,  H01L2027/11881

Abstract: According to a certain embodiment, the semiconductor integrated circuit includes: first and second power source lines disposed to extend in a first direction; a third power source line disposed in parallel to the first power supply line in a second direction, and having an electric potential equivalent to that of the second power source line; a fourth power source line disposed in parallel to the second power supply line and having an electric potential equivalent to that of the first power source line; a first transistor disposed below the first power supply line and including a first active region; a second transistor disposed below the second power source line and including a second active region; a third transistor disposed between the first active region and the third power source line and including a third active region; and a fourth transistor including a fourth active region.

公开(公告)号：US20220014191A1

公开(公告)日：2022-01-13

申请号：US17189344

申请日：2021-03-02

Applicant: Kioxia Corporation

Inventor： Koji KOHARA

IPC: H03K19/00

Abstract: According to a certain embodiment, the semiconductor device includes a circuit block and a clock circuit configured to supply a clock signal to the circuit block at a specific timing. The clock circuit includes an output circuit configured to provide the clock signal to the circuit block, and a control circuit configured to control the timing at which the output circuit provides the clock signal. A threshold voltage of at least a transistor in the output circuit using the clock signal as input/output signals is a first threshold voltage, and a threshold voltage of a transistor configuring the control circuit is a second threshold voltage higher than the first threshold voltage.

公开(公告)号：US20240194683A1

公开(公告)日：2024-06-13

申请号：US18463617

申请日：2023-09-08

Applicant: Kioxia Corporation

Inventor： Koji KOHARA

IPC: H01L27/118 ,  G06F30/392 ,  H01L27/02 ,  H03K19/20

CPC classification number: H01L27/11807 ,  G06F30/392 ,  H01L27/0207 ,  H03K19/20 ,  G06F2111/20 ,  H01L2027/1182 ,  H01L2027/11866

Abstract: According to one embodiment, a semiconductor integrated circuit includes: a first power supply line extending in a first direction; a second power supply line extending in the first direction parallel to the first power supply line; a block circuit disposed between the first and second power supply lines, and comprising a first logic circuit to which first and second inputs are supplied, a second logic circuit to which third and fourth inputs are supplied, and a third logic circuit to which outputs from the first and second logic circuits are supplied; a first wiring extending in a second direction orthogonal to the first direction; and a second wiring extending in the second direction parallel to the first wiring. Any one of the first or second input is connected to the first wiring, and any one of the third or fourth input is connected to the second wiring.