公开(公告)号：US20210225847A1

公开(公告)日：2021-07-22

申请号：US17012676

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Masaharu WADA ,  Mutsumi OKAJIMA ,  Tsuneo INABA ,  Shinji MIYANO

IPC: H01L27/108 ,  G11C11/407

Abstract: A semiconductor memory device, includes: a first region including a first memory cell array; a second region arranged with the first region; and a third region arranged with the second region and including a second memory cell array. Each memory cell array includes: a field effect transistor above a semiconductor substrate, including a gate, a source, and a drain, the gate being connected to a first wiring, and one of the source and the drain being connected to a second wiring; and a capacitor below the transistor, including a first electrode connected to the other of the source and the drain, a second, electrode facing the first electrode, and a third electrode connected to the second electrode and extending to the second region. The second region includes a conductor, the conductor connecting the third electrodes of the memory cell arrays.

公开(公告)号：US20210201980A1

公开(公告)日：2021-07-01

申请号：US17006238

申请日：2020-08-28

Applicant: KIOXIA CORPORATION

Inventor： Masaharu WADA

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C5/02 ,  G11C5/06

Abstract: According to one embodiment, a semiconductor storage device includes a first stacked portion including a first peripheral circuit and a second stacked portion above the first stacked portion. The second stacked portion including a memory cell, a word line connected to the memory cell, a bit line connected to the memory cell and the first peripheral circuit, and at least one of a second peripheral circuit connected to the bit line and a third peripheral circuit connected to the word line. The at least one of the second or third peripheral circuits including a field effect transistor having a channel layer containing an oxide semiconductor.

公开(公告)号：US20220406783A1

公开(公告)日：2022-12-22

申请号：US17547710

申请日：2021-12-10

Applicant: Kioxia Corporation

Inventor： Masaharu WADA ,  Mutsumi OKAJIMA

IPC: H01L27/108 ,  H01L29/221 ,  G11C5/02

Abstract: A semiconductor memory device includes a substrate, memory layers, a first wiring disposed at a position closer to the substrate than memory layers or a position farther from the substrate than memory layers, a transistor layer disposed between memory layers and the first wiring, and a second wiring connected to the memory layers and the transistor layer. Each of memory layers includes a memory unit, a first semiconductor layer connected between the memory unit and the second wiring, a first electrode opposed to the first semiconductor layer, a third wiring connected to the first electrode, a second semiconductor layer electrically connected to one end portion of the third wiring, and a second electrode opposed to the second semiconductor layer. The transistor layer includes a third semiconductor layer connected between the first wiring and the second wiring, and a third electrode opposed to the third semiconductor layer.

公开(公告)号：US20230197141A1

公开(公告)日：2023-06-22

申请号：US17834516

申请日：2022-06-07

Applicant: Kioxia Corporation

Inventor： Masaharu WADA

IPC: G11C11/4091

CPC classification number: G11C11/4091

Abstract: A first transistor is coupled to a capacitor. A first inverter circuit is coupled between first and second nodes, and includes a p-type second transistor and an n-type third transistor coupled at a third node. A second inverter circuit is coupled between the first and second nodes, and includes a p-type fourth transistor and an n-type fifth transistor coupled at a fourth node. A sixth transistor is coupled between gates of the fourth and fifth transistors, and the third node. A seventh transistor is coupled between gates of the second and third transistors, and the fourth node. An eighth transistor is coupled between the gate of the second transistor and the third node. A ninth transistor is coupled between the gate of the fourth transistor and the fourth node.

公开(公告)号：US20250022530A1

公开(公告)日：2025-01-16

申请号：US18768033

申请日：2024-07-10

Applicant: Kioxia Corporation

Inventor： Takeshi AOKI ,  Masaharu WADA ,  Mamoru ISHIZAKA

IPC: G11C29/44

Abstract: A memory device includes memory cells, first wirings extending along a first direction and connected to the cells, second wirings extending along a second direction and connected to the cells, the second direction intersecting the first direction, third wirings extending along a third direction and each connected to one or more second wirings, the third direction intersecting the first and second directions, sense circuits each connected to one or more third wirings, a switching circuit connected to the circuits and selectively outputting signals from the sense circuits, and a control circuit storing first addresses indicating second and third wirings connected to defective cells, and when a memory cell is selected, determining second addresses indicating second and third wirings connected to the selected cell, and based on the first and second addresses, controlling the switching circuit not to output signals from one or more sense circuits connected to the defective cells.

公开(公告)号：US20240282359A1

公开(公告)日：2024-08-22

申请号：US18582433

申请日：2024-02-20

Applicant: Kioxia Corporation

Inventor： Takeshi AOKI ,  Masaharu WADA ,  Takayuki MIYAZAKI ,  Takashi INUKAI

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C11/4087 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory includes a cell array including first and second sub arrays including memory cells and simultaneously driven in a read or a write operation. First lines are connected to the cells corresponding to one of physical rows, where the physical row is the cells arranged in a first direction in the cell array. Second lines are connected to the cells arranged in a second direction intersecting with the first direction in the cell array. A decoder selects a selection line from among the first lines in accordance with a logical row address corresponding to each of the physical rows and applies a read voltage or a write voltage to the selection line. A sense amplifier detects data from the second lines. Logical row addresses corresponding to physical rows adjacent to a certain physical row among the physical rows differ between the first sub array and the second sub array.

公开(公告)号：US20240057314A1

公开(公告)日：2024-02-15

申请号：US18448703

申请日：2023-08-11

Applicant: Kioxia Corporation

Inventor： Takeshi AOKI ,  Takayuki MIYAZAKI ,  Masaharu WADA ,  Takashi INUKAI

IPC: H10B12/00 ,  H01L29/786

CPC classification number: H10B12/33 ,  H01L29/7869 ,  H01L29/78642 ,  H10B12/48

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate and a capacitor that includes a first electrode extending in a first direction intersecting the semiconductor substrate and a second electrode facing the first electrode. A first conductive layer is above the capacitor and extends in a second direction. A semiconductor layer penetrates the first conductive layer in the first direction. A first conductor can be above or below the first conductive layer and electrically connected to the first conductive layer. A first insulating film is between the first conductive layer and the semiconductor layer. A second conductive layer extends in the second direction and is electrically connected to the first conductive layer via the first conductor.

公开(公告)号：US20230200051A1

公开(公告)日：2023-06-22

申请号：US17841529

申请日：2022-06-15

Applicant: Kioxia Corporation

Inventor： Takeshi AOKI ,  Masaharu WADA ,  Mamoru ISHIZAKA ,  Tsuneo INABA

IPC: H01L27/108 ,  G11C11/4091 ,  H01L29/786

CPC classification number: H01L27/10805 ,  H01L27/10897 ,  G11C11/4091 ,  H01L29/7869

Abstract: A semiconductor memory device comprises a memory cell array. The memory cell array comprises sub arrays. The sub array comprises: memory portions; first semiconductor layers electrically connected to memory portions; first gate electrodes respectively facing first semiconductor layers; a first wiring electrically connected to first semiconductor layers; second wirings connected to first gate electrodes; second semiconductor layers electrically connected to first end portions of second wirings; second gate electrodes facing second semiconductor layers; and a third wiring electrically connected to second semiconductor layers. The memory cell array comprises fourth wirings that extend in one direction across the sub arrays and are connected to second gate electrodes.

公开(公告)号：US20220310153A1

公开(公告)日：2022-09-29

申请号：US17472172

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Masaharu WADA

IPC: G11C11/4091 ,  G11C11/4094

Abstract: A semiconductor memory device includes a memory cell that includes a capacitor including a first and second end and a first transistor. The first transistor includes a third and fourth end, is coupled to the first end at the fourth end, and contains an oxide semiconductor. A bit line is coupled to the third end. A sense amplifier is coupled to the bit line and coupled between a first node of a first potential and a second node of a second potential lower than the first potential. A potential generator is configured to supply the second end with a fourth potential that is different from a third potential intermediate between the first potential and the second potential.

公开(公告)号：US20210082921A1

公开(公告)日：2021-03-18

申请号：US16803786

申请日：2020-02-27

Applicant: KIOXIA CORPORATION

Inventor： Masaharu WADA ,  Keiji IKEDA

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/10 ,  H01L29/24 ,  H01L29/66 ,  H01L29/78

Abstract: According to one embodiment, a semiconductor storage device includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction intersecting the first direction, and a plurality of first semiconductor transistors. Each first semiconductor transistor is respectively connected between one of the plurality of first wires and one of the plurality of second wires. Each first semiconductor transistor includes a gate electrode connected to the respective first wire and a channel layer on a first surface of the second wire and also a side surface of the respective second wire.