公开(公告)号：US20240099033A1

公开(公告)日：2024-03-21

申请号：US18465244

申请日：2023-09-12

Applicant: Kioxia Corporation

Inventor： Toshiaki SATO ,  Masaki UNNO

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device includes a plurality of sense amplifier regions, a first wiring layer including a plurality of bit lines electrically connected to a plurality of semiconductor layers, and a second wiring layer including a plurality of first wirings electrically connecting the respective plurality of sense amplifier regions to the plurality of bit lines. The semiconductor substrate includes a first region and a second region arranged in a second direction. The (n1) (n1 is an integer of 2 or more) first wirings arranged in the third direction are disposed at a position where the first region overlaps with the sense amplifier region viewed in the first direction. The (n2) (n2 is an integer of 2 or more different from n1) first wirings arranged in the third direction are disposed at a position where the second region overlaps with the other sense amplifier region viewed in the first direction.

公开(公告)号：US20230307395A1

公开(公告)日：2023-09-28

申请号：US17813812

申请日：2022-07-20

Applicant: Kioxia Corporation

Inventor： Nobuaki OKADA ,  Masaki UNNO ,  Hiroyuki TAKENAKA ,  Yoshiaki TAKAHASHI ,  Hiroshi MAEJIMA

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device comprises a first chip and a second chip bonded via bonding electrodes. The first chip comprises a semiconductor substrate. The second chip comprises: first conductive layers; semiconductor layers facing the first conductive layers; a first wiring layer including bit lines; a second wiring layer including wirings; and a third wiring layer including first bonding electrodes. The wirings each comprise: a first portion provided in a region overlapping one of the bit lines, and is electrically connected to the one of the bit lines; and a second portion provided in a region overlapping one of the first bonding electrodes, and is connected to the one of the first bonding electrodes. At least some of these wirings comprise a third portion connected to one end portion in a second direction of the first portion and one end portion in the second direction of the second portion.

公开(公告)号：US20220059433A1

公开(公告)日：2022-02-24

申请号：US17182285

申请日：2021-02-23

Applicant: Kioxia Corporation

Inventor： Masaki UNNO

IPC: H01L23/48 ,  H01L25/18 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor memory device includes a substrate including a first to a fourth region, first conductive layers from the first to second region, second conductive layers from the fourth to second region, third conductive layers from the first to third region, fourth conductive layers from the fourth to third region, a first semiconductor column opposed to the first and third conductive layers in the first region, a second semiconductor column opposed to the second and fourth conductive layers in the fourth region, first and second contacts connected to the first and the second conductive layers in the second region, third and fourth contacts connected to the third and fourth conductive layers in the third region, first wirings connected to the first and second contacts in the second region, and second wirings connected to the third and fourth contacts in the third region.

公开(公告)号：US20210174879A1

公开(公告)日：2021-06-10

申请号：US17009389

申请日：2020-09-01

Applicant: KIOXIA CORPORATION

Inventor： Takeshi HIOKA ,  Naofumi ABIKO ,  Masaki UNNO

IPC: G11C16/14 ,  G11C11/56 ,  G11C16/04

Abstract: A semiconductor memory device includes a first memory cell, a first select transistor between the first memory cell and a source line, a second select transistor between the first memory cell and a bit line, a third select transistor between the source line and the bit line, and a control circuit. During an erase operation, the control circuit is configured to apply a first voltage to the source line, apply a second voltage lower than the first voltage to a gate of the third select transistor while applying the first voltage to the source line to cause a third voltage to be applied to the bit line, and apply a fourth voltage lower than the third voltage to the gate of the second select transistor while the third voltage is applied to the bit line.