公开(公告)号：US20210050048A1

公开(公告)日：2021-02-18

申请号：US16799196

申请日：2020-02-24

Applicant: KIOXIA CORPORATION

Inventor： Rui ITO ,  Takeshi HIOKA ,  Takuyo KODAMA

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/56

Abstract: According to one embodiment, a sense amplifier circuit includes an amplifier having an input terminal connected to a sense node, and a first capacitor configured to be connected in a feedback path of the amplification transistor and to a bit line of a memory cell via the sense node, the first capacitor configured to supply a current to the memory cell and integrate the current when the memory cell is read.

公开(公告)号：US20230290417A1

公开(公告)日：2023-09-14

申请号：US17899951

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Takeshi HIOKA

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/28 ,  G11C16/0483 ,  G11C16/14

Abstract: A semiconductor storage device includes a plurality of word line layers stacked above one another in a first direction, a memory pillar having a columnar body penetrating the plurality of the word line layers, wherein each portion of the memory pillar intersecting the word line layers functions as a memory cell transistor, a source line layer to which an end of the memory pillar is connected, an acquisition circuit configured to acquire a voltage of the source line layer, and a first adjustment circuit configured to adjust the voltage of the source line layer to a predetermined target voltage based on the acquired voltage. The acquisition circuit includes a dummy pillar having a columnar body penetrating the plurality of word line layers and having an end connected to the source line layer, wherein each portion of the dummy pillar intersecting the word line layers functions as a dummy transistor.

公开(公告)号：US20230062330A1

公开(公告)日：2023-03-02

申请号：US18054746

申请日：2022-11-11

Applicant: Kioxia Corporation

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI ,  Takeshi HIOKA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

公开(公告)号：US20210264989A1

公开(公告)日：2021-08-26

申请号：US17008337

申请日：2020-08-31

Applicant: KIOXIA CORPORATION

Inventor： Kosuke YANAGIDAIRA ,  Takuyo KODAMA ,  Takeshi HIOKA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08

Abstract: A semiconductor storage device includes first and second memory cells, first and second word lines connected to the first and second memory cells, respectively, a bit line connected to the first and second memory cells, and a sense amplifier including a sense node. During a first read, a controller applies a first read voltage to the second word line and determines a read result. During a second read, the controller discharges the sense node for a first time period while applying a second read voltage to the first word line to determine a first read result, and discharges the sense node for a second time period while applying the second read voltage to determine a second read result. The controller determines read data based on the first read result, the second read result, and the read result of the second memory cell.

公开(公告)号：US20210174879A1

公开(公告)日：2021-06-10

申请号：US17009389

申请日：2020-09-01

Applicant: KIOXIA CORPORATION

Inventor： Takeshi HIOKA ,  Naofumi ABIKO ,  Masaki UNNO

IPC: G11C16/14 ,  G11C11/56 ,  G11C16/04

Abstract: A semiconductor memory device includes a first memory cell, a first select transistor between the first memory cell and a source line, a second select transistor between the first memory cell and a bit line, a third select transistor between the source line and the bit line, and a control circuit. During an erase operation, the control circuit is configured to apply a first voltage to the source line, apply a second voltage lower than the first voltage to a gate of the third select transistor while applying the first voltage to the source line to cause a third voltage to be applied to the bit line, and apply a fourth voltage lower than the third voltage to the gate of the second select transistor while the third voltage is applied to the bit line.

公开(公告)号：US20250037775A1

公开(公告)日：2025-01-30

申请号：US18919022

申请日：2024-10-17

Applicant: Kioxia Corporation

Inventor： Takeshi HIOKA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26

Abstract: A semiconductor memory device includes first and second memory cell transistors between first and second select transistors, third and fourth memory cell transistors between third and fourth select transistors, a first word line for first and third memory cell transistors, a second word line for second and fourth memory cell transistors, first to fourth selection gate lines respectively for first through fourth select transistors, a bit line, and a source line. During a read operation, while a voltage applied to the second word line is boosted, voltages applied to the first word line and the third and fourth selection gate line are also boosted, after which the voltage applied to the first word line is lowered, and the third and fourth selection gate lines are discharged. After the time the third and fourth selection gate lines are discharged, voltages applied to the bit line and the source line are boosted.

公开(公告)号：US20230317184A1

公开(公告)日：2023-10-05

申请号：US17899971

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Takeshi HIOKA ,  Toshifumi WATANABE

IPC: G11C16/34 ,  G11C16/10 ,  G11C7/06

CPC classification number: G11C16/3459 ,  G11C7/06 ,  G11C16/3404 ,  G11C16/102

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected to the plurality of memory cells, a plurality of bit lines connected respectively to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller configured to execute a write operation in a plurality of program loops each including a program operation and a verify operation. The sense amplifier is configured to apply a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage to first, second, third, and fourth bit lines of the plurality of bit lines, respectively, while a program voltage is applied to the word line in the program operation.

公开(公告)号：US20240087656A1

公开(公告)日：2024-03-14

申请号：US18332753

申请日：2023-06-12

Applicant: Kioxia Corporation

Inventor： Katsuaki ISOBE ,  Takeshi HIOKA ,  Mario SAKO

IPC: G11C16/26 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0483

Abstract: A semiconductor memory device includes a first memory cell transistor, a first bit line electrically coupled to the first memory cell transistor, a first sense amplifier, and a first latch circuit. The first sense amplifier includes a first node coupled to the first bit line, a first transistor including one end electrically coupled to the first latch circuit, a second node coupled to a gate of the first transistor, and a second transistor coupled between the first and second nodes. The second transistor is in an ON state during an operation of transferring a charge from the first bit line to the first and second nodes in accordance with data of the first memory cell transistor. The second transistor is in an OFF state during an operation of transferring data of the second node to the first latch circuit.

公开(公告)号：US20210335418A1

公开(公告)日：2021-10-28

申请号：US17198375

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Kosuke YANAGIDAIRA ,  Hiroshi TSUBOUCHI ,  Takeshi HIOKA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a word line, a bit line, a first transistor, a second transistor and a driver. The word line is electrically coupled to a gate of the memory cell. The bit line is electrically coupled to one end of the memory cell. The first transistor includes a first gate electrically coupled to the bit line. The second transistor is coupled to a first end of the first transistor. The driver is configured to apply a voltage to the first gate of the first transistor. In a read operation, the driver varies a voltage to be applied to the first gate of the first transistor based on a read voltage applied to the word line.

公开(公告)号：US20210174882A1

公开(公告)日：2021-06-10

申请号：US17017726

申请日：2020-09-11

Applicant: Kioxia Corporation

Inventor： Yousuke HAGIWARA ,  Kensuke YAMAMOTO ,  Takeshi HIOKA ,  Satoshi INOUE

IPC: G11C16/30 ,  G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G11C16/04

Abstract: In general, according to one embodiment, an output circuit includes first to third power supply lines, a pad, first to second transistors, and a first circuit. A first end of the first transistor is coupled to the first power supply line. A second end of the first transistor is coupled to the pad. A first end of the second transistor is coupled to the second power supply line. A second end of the second transistor is coupled to the pad. The first circuit is coupled to each of the third power supply line and a gate of the first transistor. In a first case, the first circuit applies a fourth voltage to the gate of the first transistor.