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公开(公告)号：US20250095748A1
公开(公告)日：2025-03-20
申请号：US18967232
申请日：2024-12-03
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA , Akihiro IMAMOTO , Toshifumi WATANABE , Mami KAKOI , Kohei MASUDA , Masahiro YOSHIHARA , Naofumi ABIKO
Abstract: A semiconductor memory device includes plural planes each including plural blocks each including a memory cell, a voltage generator which supplies power to the plural planes, an input/output circuit which receives a command set sent from a memory controller to the semiconductor memory device, and a sequencer which executes an operation in response to the command set. Upon receiving a first command set instructing execution of a first operation, the sequencer executes the first operation. Upon receiving a command set instructing operation of a second operation during execution of the first operation, the sequencer executes the first and second operations in parallel. Upon receiving a third command set instructing execution of a third operation during execution of the first operation, the sequencer suspends the first operation, executes the third operation, and resumes the first operation upon completion of the third operation.
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公开(公告)号：US20220358991A1
公开(公告)日：2022-11-10
申请号：US17873427
申请日：2022-07-26
Applicant: KIOXIA CORPORATION
Inventor： Toshifumi WATANABE , Naofumi ABIKO
IPC: G11C11/4074 , G11C11/4076 , G11C11/56 , G11C11/408 , G11C11/4094
Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
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公开(公告)号：US20230186984A1
公开(公告)日：2023-06-15
申请号：US17896929
申请日：2022-08-26
Applicant: KIOXIA CORPORATION
Inventor： Naofumi ABIKO
CPC classification number: G11C11/5628 , G11C11/5642 , G11C11/5671 , G11C16/10 , G11C16/26 , G11C16/3459
Abstract: A semiconductor memory device includes memory cell transistors and a control circuit. In a write operation, the control circuit executes multiple loops each including a program operation, a verify operation, and a bit scan operation. In the bit scan operation, the control circuit performs, a first process of generating verify result data in parallel for a group of memory cell transistors having different target threshold voltage states, the verify result data for each memory cell transistor in the group indicating whether the memory cell transistor has reached its target threshold voltage state, and a second process of calculating for each of the target threshold voltage states, the number of memory cell transistors that have not reached their target threshold voltage states.
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公开(公告)号：US20220310180A1
公开(公告)日：2022-09-29
申请号：US17807034
申请日：2022-06-15
Applicant: KIOXIA CORPORATION
Inventor： Yoshihiko KAMATA , Naofumi ABIKO
IPC: G11C16/34 , G11C11/4094 , G11C7/12 , G11C16/04 , G11C11/56 , G11C16/32 , G11C16/08 , G11C16/24 , G11C16/26
Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.
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公开(公告)号：US20220284972A1
公开(公告)日：2022-09-08
申请号：US17459712
申请日：2021-08-27
Applicant: KIOXIA CORPORATION
Inventor： Emiri TAKADA , Naofumi ABIKO
Abstract: A semiconductor storage device includes a memory cell array includes a plurality of memory cell transistors, a plurality of word lines connected to gates of the memory cell transistors, a voltage generation circuit configured to generate a voltage applied to each of the word lines, and a control circuit configured to control an operation of the memory cell array. In a write operation for writing data to the memory cell array that includes multiple loops of a program operation and a verify operation, the control circuit controls an operation of the voltage generation circuit so that a rate of increase of a voltage applied to a non-selected word line at a beginning of the verify operation is different for at least two of the loops.
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Patent Agency Ranking
公开(公告)号：US20230052383A1
公开(公告)日：2023-02-16
申请号：US17973549
申请日：2022-10-26
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA , Akihiro IMAMOTO , Toshifumi WATANABE , Mami KAKOI , Kohei MASUDA , Masahiro YOSHIHARA , Naofumi ABIKO
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
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公开(公告)号：US20210225424A1
公开(公告)日：2021-07-22
申请号：US17222969
申请日：2021-04-05
Applicant: KIOXIA CORPORATION
Inventor： Toshifumi WATANABE , Naofumi ABIKO
IPC: G11C11/4074 , G11C11/4076 , G11C11/56 , G11C11/408 , G11C11/4094
Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
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公开(公告)号：US20210202007A1
公开(公告)日：2021-07-01
申请号：US17200996
申请日：2021-03-15
Applicant: Kioxia Corporation
Inventor： Akio SUGAHARA , Akihiro IMAMOTO , Toshifumi WATANABE , Mami KAKOI , Kohei MASUDA , Masahiro YOSHIHARA , Naofumi ABIKO
Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation, and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.
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公开(公告)号：US20240046974A1
公开(公告)日：2024-02-08
申请号：US18490148
申请日：2023-10-19
Applicant: Kioxia Corporation
Inventor： Toshifumi WATANABE , Naofumi ABIKO
IPC: G11C11/4074 , G11C11/4076 , G11C11/56 , G11C11/408 , G11C11/4094
CPC classification number: G11C11/4074 , G11C11/4076 , G11C11/5642 , G11C11/4085 , G11C11/5628 , G11C11/4094 , G11C16/0483
Abstract: A semiconductor memory device includes a memory cell, a word line connected to the memory cell, a source line connected to the memory cell, a bit line connected to the memory cell, and a control circuit configured to perform a read operation on the memory cell. During the read operation, the control circuit applies to the word line a first voltage, a second voltage greater than the first voltage after applying the first voltage, and a third voltage greater than the first voltage and smaller than the second voltage after applying the second voltage, and applies to the source line a fourth voltage according to a timing at which the second voltage is applied to the word line, a fifth voltage smaller than the fourth voltage after applying the fourth voltage, and a sixth voltage greater than the fifth voltage after applying the fifth voltage.
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公开(公告)号：US20240029805A1
公开(公告)日：2024-01-25
申请号：US18482103
申请日：2023-10-06
Applicant: KIOXIA CORPORATION
Inventor： Yoshihiko KAMATA , Naofumi ABIKO
IPC: G11C16/34 , G11C11/4094 , G11C7/12 , G11C16/04 , G11C11/56 , G11C16/32 , G11C16/08 , G11C16/24 , G11C16/26
CPC classification number: G11C16/3445 , G11C11/4094 , G11C16/3459 , G11C7/12 , G11C16/0475 , G11C16/0483 , G11C11/5635 , G11C16/32 , G11C16/08 , G11C16/24 , G11C16/26 , G11C2211/5641 , G11C8/08
Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a first word line, first and second sense amplifiers, first and second bit lines, a controller. The first and second sense amplifiers each include first and second transistors. The first bit line is connected between the first memory cell and the first transistor. The second bit line is connected between the second memory cell and the second transistor. In the read operation, the controller is configured to apply a kick voltage to the first word line before applying the read voltage to the first word line, and to apply a first voltage to a gate of the first transistor and a second voltage to a gate of the second transistor while applying the kick voltage to the first word line.
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