公开(公告)号：US11189348B2

公开(公告)日：2021-11-30

申请号：US17009389

申请日：2020-09-01

Applicant: KIOXIA CORPORATION

Inventor： Takeshi Hioka ,  Naofumi Abiko ,  Masaki Unno

IPC: G11C16/14 ,  G11C11/56 ,  G11C16/04 ,  H01L27/11582 ,  H01L27/11556

Abstract: A semiconductor memory device includes a first memory cell, a first select transistor between the first memory cell and a source line, a second select transistor between the first memory cell and a bit line, a third select transistor between the source line and the bit line, and a control circuit. During an erase operation, the control circuit is configured to apply a first voltage to the source line, apply a second voltage lower than the first voltage to a gate of the third select transistor while applying the first voltage to the source line to cause a third voltage to be applied to the bit line, and apply a fourth voltage lower than the third voltage to the gate of the second select transistor while the third voltage is applied to the bit line.

公开(公告)号：US11910609B2

公开(公告)日：2024-02-20

申请号：US17182285

申请日：2021-02-23

Applicant: Kioxia Corporation

Inventor： Masaki Unno

IPC: H10B43/10 ,  H10B43/27 ,  H10B43/50 ,  H10B43/40 ,  H01L25/18

CPC classification number: H10B43/40 ,  H01L25/18 ,  H10B43/10 ,  H10B43/27 ,  H10B43/50

Abstract: A semiconductor memory device includes a substrate including a first to a fourth region, first conductive layers from the first to second region, second conductive layers from the fourth to second region, third conductive layers from the first to third region, fourth conductive layers from the fourth to third region, a first semiconductor column opposed to the first and third conductive layers in the first region, a second semiconductor column opposed to the second and fourth conductive layers in the fourth region, first and second contacts connected to the first and the second conductive layers in the second region, third and fourth contacts connected to the third and fourth conductive layers in the third region, first wirings connected to the first and second contacts in the second region, and second wirings connected to the third and fourth contacts in the third region.