公开(公告)号：US11923324B2

公开(公告)日：2024-03-05

申请号：US17190479

申请日：2021-03-03

Applicant: Kioxia Corporation

Inventor： Masayuki Akou

IPC: H01L23/00 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L24/05 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40 ,  H01L2224/05025

Abstract: A semiconductor memory device includes a substrate, a memory cell array separated from the substrate, and a plurality of first bonding pad electrodes away from the memory cell array. The substrate includes a plurality of first and second regions arranged alternately. The memory cell array includes a plurality of conductive layers extending across the plurality of first and second regions, a plurality of semiconductor layers disposed in the plurality of first regions, and a plurality of first contacts disposed in the plurality of second regions. When a distance between a center position of the first bonding pad electrode and a center position of the first contact closest to the first bonding pad electrode is defined as a first distance, a difference between a largest first distance and a smallest first distance among a plurality of first distances is 400 nm or less.

公开(公告)号：US11302696B2

公开(公告)日：2022-04-12

申请号：US16798979

申请日：2020-02-24

Applicant: KIOXIA CORPORATION

Inventor： Hiroyuki Kutsukake ,  Masayuki Akou

IPC: H01L27/092 ,  H01L29/417

Abstract: A semiconductor device includes: two first semiconductor regions of a first conductivity type spaced apart from each other; a second semiconductor region of a second conductivity type provided between the two first semiconductor regions; a first insulator region surrounding the two first semiconductor regions and the second semiconductor region; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the second conductivity type, the fourth semiconductor region surrounding the third semiconductor region and the first insulator region and having an impurity concentration of the second conductivity type lower than an impurity concentration of the third semiconductor region; a second insulator region that surrounds the fourth semiconductor region; a conductor layer provided over the second semiconductor region; two first contact plugs; a second contact plug provided on the conductor layer; and a third contact plug provided on the third semiconductor region.

公开(公告)号：US11251122B2

公开(公告)日：2022-02-15

申请号：US16984208

申请日：2020-08-04

Applicant: Kioxia Corporation

Inventor： Masayuki Akou ,  Mitsuhiro Noguchi ,  Yuuichi Tatsumi

IPC: H01L23/528 ,  H01L27/11526 ,  H01L27/11573 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor device includes: wiring layers laminated in a first direction and including conducting members; and a second wiring layer including a bonding pad electrode. The first wiring layers each include a bonding pad area. The bonding pad area overlaps with the bonding pad electrode viewed in the first direction. The conducting member is absent in an area inside a first imaginary circle with a first point as a midpoint in the bonding pad area. The conducting members are disposed in an area outside a second imaginary circle in the bonding pad area. The second imaginary circle has the first point as a midpoint and has a radius equal to or more than a radius of the first imaginary circle. When the radius of the first imaginary circle is denoted as R1 and the radius of the second imaginary circle is denoted as R2, R2/R1 is smaller than 1/cos(π/4).

公开(公告)号：US11482489B2

公开(公告)日：2022-10-25

申请号：US16990793

申请日：2020-08-11

Applicant: KIOXIA CORPORATION

Inventor： Shingo Nakajima ,  Ryota Asada ,  Hidenobu Nagashima ,  Masayuki Akou

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11582

Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.