公开(公告)号：US11670631B2

公开(公告)日：2023-06-06

申请号：US17189744

申请日：2021-03-02

Applicant: Kioxia Corporation

Inventor： Hiroyuki Kutsukake

IPC: H01L27/088 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L27/088

Abstract: A semiconductor device includes first, second, third, and fourth active regions provided in an substrate, each of which includes a central portion, first and second portions provided at opposite sides of the central portion in a first direction, and third and fourth portions provided at opposite sides of the central portion in a second direction orthogonal to the first direction. An end portion of the first portion of the first active region faces a side portion of the fourth portion of the fourth active region, an end portion of which faces aside portion of the second portion of the second active region. An end portion of the second portion of the second active region faces a side portion of the third portion of the third active region, an end portion of which faces a side portion of the first portion of the first active region.

公开(公告)号：USRE49274E1

公开(公告)日：2022-11-01

申请号：US16284203

申请日：2019-02-25

Applicant: KIOXIA CORPORATION

Inventor： Dai Nakamura ,  Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Takeshi Shimane ,  Mitsuhiro Noguchi ,  Koji Hosono ,  Masaru Koyanagi ,  Takashi Aoi

IPC: G11C16/04 ,  G11C16/24

Abstract: A non-volatile semiconductor storage device includes: a memory cell array having memory cells arranged therein, the memory cells storing data in a non-volatile manner; and a plurality of transfer transistors transferring a voltage to the memory cells, the voltage to be supplied for data read, write and erase operations with respect to the memory cells. Each of the transfer transistors includes: a gate electrode formed on a semiconductor substrate via a gate insulation film; and diffusion layers formed to sandwich the gate electrode therebetween and functioning as drain/source layers. Upper layer wirings are provided above the diffusion layers and provided with a predetermined voltage to prevent depletion of the diffusion layers at least when the transfer transistors become conductive.

公开(公告)号：US12178049B2

公开(公告)日：2024-12-24

申请号：US17891386

申请日：2022-08-19

Applicant: Kioxia Corporation

Inventor： Hiroyuki Kutsukake

IPC: H10B41/23 ,  G11C16/08 ,  G11C16/26 ,  H10B41/35 ,  H10B43/23 ,  H10B43/35

Abstract: A semiconductor storage device includes a semiconductor substrate including a first region, a second region, and a third region, located apart from each other in such an order in a first direction in an element region. Each of the first to third regions including a source and/or drain region. The semiconductor storage device further includes a first conductor layer provided above the element region and having a first opening; a second conductor layer provided above the element region, having a second opening, and located apart from the first conductor layer in the first direction; a first contact, in the first opening, that is connected to the first region; a second contact, in the second opening, that is connected to the third region; a first memory cell connected to the first contact; and a second memory cell connected to the second contact.

公开(公告)号：US11937432B2

公开(公告)日：2024-03-19

申请号：US17459844

申请日：2021-08-27

Applicant: Kioxia Corporation

Inventor： Hiroyuki Kutsukake

IPC: H10B43/40 ,  H10B43/27 ,  H01L29/786

CPC classification number: H10B43/40 ,  H10B43/27 ,  H01L29/786 ,  H01L29/78651

Abstract: Embodiments provide a semiconductor device capable of being highly integrated.
A semiconductor device includes a semiconductor substrate, a first insulating layer formed toward an inside of a semiconductor substrate from a main surface of the semiconductor substrate, and a transistor formed on the first insulating layer. the transistor has a first semiconductor layer formed on the first insulating layer to be insulated from the semiconductor substrate, a second insulating layer provided on a second region among of a first region, the second region, and a third region sequentially arranged in a first direction along the main surface of the first semiconductor layer, and a first conductive layer provided on the second insulating layer. a first contact is connected to the first region of the first semiconductor layer, a second contact is connected to the third region of the first semiconductor layer, and a third contact is connected to the first conductive layer.

公开(公告)号：US11302696B2

公开(公告)日：2022-04-12

申请号：US16798979

申请日：2020-02-24

Applicant: KIOXIA CORPORATION

Inventor： Hiroyuki Kutsukake ,  Masayuki Akou

IPC: H01L27/092 ,  H01L29/417

Abstract: A semiconductor device includes: two first semiconductor regions of a first conductivity type spaced apart from each other; a second semiconductor region of a second conductivity type provided between the two first semiconductor regions; a first insulator region surrounding the two first semiconductor regions and the second semiconductor region; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the second conductivity type, the fourth semiconductor region surrounding the third semiconductor region and the first insulator region and having an impurity concentration of the second conductivity type lower than an impurity concentration of the third semiconductor region; a second insulator region that surrounds the fourth semiconductor region; a conductor layer provided over the second semiconductor region; two first contact plugs; a second contact plug provided on the conductor layer; and a third contact plug provided on the third semiconductor region.