公开(公告)号：US20220068964A1

公开(公告)日：2022-03-03

申请号：US17204015

申请日：2021-03-17

Applicant: Kioxia Corporation

Inventor： Tomohiro KUKI ,  Tatsufumi HAMADA ,  Shinichi SOTOME ,  Yosuke MITSUNO ,  Muneyuki TSUDA

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/306 ,  H01L27/11556 ,  H01L27/11597

Abstract: According to one embodiment, a semiconductor storage device includes a substrate, a first electric charge holder, and a channel layer. At least a part of the first electric charge holder is curved in a first cross section along a surface of the substrate. The channel layer is inside the first electric charge holder in the first cross section. At least a part of the channel layer is curved in the first cross section. The first electric charge holder has a curvature varying in accordance with a position in the first cross section. The channel layer has a film thickness varying in accordance with the curvature of the first electric charge holder in the first cross section.

公开(公告)号：US20230031132A1

公开(公告)日：2023-02-02

申请号：US17644816

申请日：2021-12-17

Applicant: Kioxia Corporation

Inventor： Muneyuki TSUDA

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: A semiconductor device according to an embodiment includes a plurality of conductive layers stacked apart from each other and extending in a plate shape in a direction crossing a stacking direction; a channel body including a semiconductor film and penetrating the plurality of conductive layers; a memory film including a charge accumulation film and provided between the plurality of conductive layers and the channel body; and a high dielectric constant (high-k) film arranged between the plurality of conductive layers and the memory film while being divided in a circumferential direction surrounding the memory film.

公开(公告)号：US20220085063A1

公开(公告)日：2022-03-17

申请号：US17201094

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Muneyuki TSUDA

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11556

Abstract: A semiconductor memory device includes: a plurality of conductive layers; a plurality of insulating layers; a semiconductor layer; and a plurality of electric charge accumulating layers. A conductive layer of the plurality of conductive layers has a first width at a first position where a surface opposed to the semiconductor layer is disposed and has a second width at a second position farther from an electric charge accumulating layer of the plurality of electric charge accumulating layers than the first position. The first width is smaller than the second width, a third width as a maximum width in the electric charge accumulating layer is equal to the first width or smaller than the first width, and the surface at the first position of the conductive layer has no portion that approaches the electric charge accumulating layer from a center to both ends.

公开(公告)号：US20210272640A1

公开(公告)日：2021-09-02

申请号：US17014776

申请日：2020-09-08

Applicant: KIOXIA CORPORATION

Inventor： Tatsuo OGURA ,  Takashi KURUSU ,  Muneyuki TSUDA ,  Hiroshi TAKEDA ,  Nayuta KARIYA

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04

Abstract: A semiconductor memory device includes a plurality of conductive layers, a semiconductor layer opposed to the plurality of conductive layers, and an electric charge accumulation portion disposed between the semiconductor layer and the plurality of conductive layers. The electric charge accumulation portion includes a plurality of first electric charge accumulation portions opposed to the plurality of conductive layers, and a plurality of second electric charge accumulation portions disposed in positions different from the plurality of first electric charge accumulation portions. A distance between the first electric charge accumulation portion and the semiconductor layer is smaller than a distance between the second electric charge accumulation portion and the semiconductor layer. A distance between the second electric charge accumulation portion and the conductive layers is smaller than a distance between the first electric charge accumulation portion and the conductive layers.

公开(公告)号：US20210358552A1

公开(公告)日：2021-11-18

申请号：US17201080

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Nayuta KARIYA ,  Muneyuki TSUDA

IPC: G11C16/10 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

Abstract: A semiconductor memory device includes first conductive layers, second conductive layers, a semiconductor layer disposed between the first conductive layers and the second conductive layers, and a charge storage layer including a first part disposed between the first conductive layers and the semiconductor layer and a second part disposed between the second conductive layers and the semiconductor layer. This semiconductor memory device is configured to execute a first write operation in which a first program voltage is supplied to a third conductive layer which is one of the first conductive layers and a write pass voltage is supplied to a fourth conductive layer which is another of the first conductive layers, and a second write operation in which a second program voltage is supplied to the third conductive layer and to the fourth conductive layer.

公开(公告)号：US20210043260A1

公开(公告)日：2021-02-11

申请号：US16787368

申请日：2020-02-11

Applicant: Kioxia Corporation

Inventor： Muneyuki TSUDA

IPC: G11C16/16 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

Abstract: A semiconductor memory device comprises: a memory cell array comprising a plurality of conductive layers, a semiconductor layer, and charge accumulating sections; and a control circuit that executes an erase operation. The plurality of conductive layers include: one or a plurality not adjacent in a first direction, of first conductive layers; and one or a plurality not adjacent in the first direction, of second conductive layers different from the first conductive layers. The erase operation includes an erase mode that executes a first erase flow. The first erase flow includes: a first write operation in which a first program voltage is applied to the plurality of conductive layers; a first erase operation that is executed after the first write operation, and in which, while a first voltage is applied to the first conductive layer, a voltage higher than the first voltage is applied to the second conductive layer; and a second erase operation that is executed after the first erase operation, and in which, while the first voltage is applied to the second conductive layer, a voltage higher than the first voltage is applied to the first conductive layer.