公开(公告)号：US20230069251A1

公开(公告)日：2023-03-02

申请号：US17695060

申请日：2022-03-15

Applicant: Kioxia Corporation

Inventor： Nayuta KARIYA

IPC: G11C16/14 ,  G11C16/04 ,  G11C5/06 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor memory device includes first conductive layers arranged in a first direction, a second conductive layer disposed at a position overlapping with the first conductive layers viewed from the first direction, a third conductive layer disposed at a position overlapping with the first conductive layers viewed from the first direction and arranged with the second conductive layer in a second direction intersecting with the first direction, a first semiconductor column opposed to the first conductive layers and the second conductive layer, a second semiconductor column opposed to the first conductive layers and the third conductive layer, and a fourth conductive layer disposed between the second conductive layer and the third conductive layer. The fourth conductive layer has a length in the second direction smaller than a length of the second conductive layer in the second direction and a length of the third conductive layer in the second direction.

公开(公告)号：US20210358552A1

公开(公告)日：2021-11-18

申请号：US17201080

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Nayuta KARIYA ,  Muneyuki TSUDA

IPC: G11C16/10 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26

Abstract: A semiconductor memory device includes first conductive layers, second conductive layers, a semiconductor layer disposed between the first conductive layers and the second conductive layers, and a charge storage layer including a first part disposed between the first conductive layers and the semiconductor layer and a second part disposed between the second conductive layers and the semiconductor layer. This semiconductor memory device is configured to execute a first write operation in which a first program voltage is supplied to a third conductive layer which is one of the first conductive layers and a write pass voltage is supplied to a fourth conductive layer which is another of the first conductive layers, and a second write operation in which a second program voltage is supplied to the third conductive layer and to the fourth conductive layer.

公开(公告)号：US20210272640A1

公开(公告)日：2021-09-02

申请号：US17014776

申请日：2020-09-08

Applicant: KIOXIA CORPORATION

Inventor： Tatsuo OGURA ,  Takashi KURUSU ,  Muneyuki TSUDA ,  Hiroshi TAKEDA ,  Nayuta KARIYA

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04

Abstract: A semiconductor memory device includes a plurality of conductive layers, a semiconductor layer opposed to the plurality of conductive layers, and an electric charge accumulation portion disposed between the semiconductor layer and the plurality of conductive layers. The electric charge accumulation portion includes a plurality of first electric charge accumulation portions opposed to the plurality of conductive layers, and a plurality of second electric charge accumulation portions disposed in positions different from the plurality of first electric charge accumulation portions. A distance between the first electric charge accumulation portion and the semiconductor layer is smaller than a distance between the second electric charge accumulation portion and the semiconductor layer. A distance between the second electric charge accumulation portion and the conductive layers is smaller than a distance between the first electric charge accumulation portion and the conductive layers.