公开(公告)号：US20250098165A1

公开(公告)日：2025-03-20

申请号：US18884125

申请日：2024-09-13

Applicant: Kioxia Corporation

Inventor： Fumie KIKUSHIMA ,  Michiko ISHIDA ,  Yosuke MURAKAMI ,  Hideomi AOIKE ,  Tatsuya ISHIKAWA ,  Ryo YOUGAUCHI ,  Tatsuo OGURA

IPC: H10B43/27 ,  H10B43/10

Abstract: In one embodiment, a semiconductor memory device includes a stacked body of a first conductive films and first insulation films alternately stacked with each other in a first direction. A plurality of columnar bodies is in the stacked body. Each columnar body includes a first semiconductor part extending in the first direction, a first insulation part between the first semiconductor part and the stacked body, a second insulation part between the first insulation part and the stacked body, third insulation parts between the second insulation part and the first conductive films, and fourth insulation parts between the second insulation part and the first insulation films. Each second insulation part has first portions between the first insulation part and the first conductive films and second portions between the first insulation part and the first insulation film. The second portions are thinner than the first portions in a second direction.

公开(公告)号：US20250095743A1

公开(公告)日：2025-03-20

申请号：US18829434

申请日：2024-09-10

Applicant: Kioxia Corporation

Inventor： Tatsuo OGURA ,  Masaki KONDO ,  Takashi MAEDA

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  H01L25/065 ,  H10B43/30 ,  H10B43/40

Abstract: A semiconductor memory device includes: a first conductive layer; and a second conductive layer adjacent to the first conductive layer. Write loops each include: a first program operation that applies the first conductive layer with a program voltage and applies a bit line with a first bit line voltage; and a second program operation that applies the first conductive layer with the program voltage and applies the bit line with a second bit line voltage larger than the first bit line voltage. The write operation includes a state judging operation that judges whether a memory cell corresponding to the semiconductor layer and the second conductive layer has been controlled to a Low-state, or not. When the memory cell has been controlled to the Low-state, the first program operation is executed, and when the memory cell has not been controlled to the Low-state, the second program operation is executed.

公开(公告)号：US20210272640A1

公开(公告)日：2021-09-02

申请号：US17014776

申请日：2020-09-08

Applicant: KIOXIA CORPORATION

Inventor： Tatsuo OGURA ,  Takashi KURUSU ,  Muneyuki TSUDA ,  Hiroshi TAKEDA ,  Nayuta KARIYA

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/12 ,  G11C16/26 ,  G11C16/30 ,  G11C16/04

Abstract: A semiconductor memory device includes a plurality of conductive layers, a semiconductor layer opposed to the plurality of conductive layers, and an electric charge accumulation portion disposed between the semiconductor layer and the plurality of conductive layers. The electric charge accumulation portion includes a plurality of first electric charge accumulation portions opposed to the plurality of conductive layers, and a plurality of second electric charge accumulation portions disposed in positions different from the plurality of first electric charge accumulation portions. A distance between the first electric charge accumulation portion and the semiconductor layer is smaller than a distance between the second electric charge accumulation portion and the semiconductor layer. A distance between the second electric charge accumulation portion and the conductive layers is smaller than a distance between the first electric charge accumulation portion and the conductive layers.