公开(公告)号：US20250056845A1

公开(公告)日：2025-02-13

申请号：US18928394

申请日：2024-10-28

Applicant: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION

Inventor： Dae Hwan KIM ,  Dong Yeon KANG ,  Jun Tae JANG ,  Shin Young PARK ,  Hyun Kyu LEE ,  Sung Jin CHOI ,  Dong Myoung KIM ,  Wonjung KIM

IPC: H01L29/78 ,  G06N3/063 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L29/788

Abstract: Disclosed is a synaptic transistor, including a substrate, an expansion gate electrode disposed to extend in one direction on the substrate, a gate insulating layer including ions, covering the expansion gate electrode, and disposed on the substrate, a channel layer disposed on the gate insulating layer to correspond to one end of the expansion gate electrode, source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the gate insulating layer, and a pad electrode disposed on the gate insulating layer to correspond to the other end of the expansion gate electrode.

公开(公告)号：US20220077314A1

公开(公告)日：2022-03-10

申请号：US17462554

申请日：2021-08-31

Applicant: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION

Inventor： Dae Hwan KIM ,  Dong Yeon KANG ,  Jun Tae JANG ,  Shin Young PARK ,  Hyun Kyu LEE ,  Sung Jin CHOI ,  Dong Myoung KIM

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/788 ,  H01L21/02 ,  H01L29/66 ,  G06N3/063

Abstract: Disclosed is a synaptic transistor, including a substrate, an expansion gate electrode disposed to extend in one direction on the substrate, a gate insulating layer including ions, covering the expansion gate electrode, and disposed on the substrate, a channel layer disposed on the gate insulating layer to correspond to one end of the expansion gate electrode, source and drain electrodes spaced apart from each other, covering both ends of the channel layer, and disposed on the gate insulating layer, and a pad electrode disposed on the gate insulating layer to correspond to the other end of the expansion gate electrode.

公开(公告)号：US20150171226A1

公开(公告)日：2015-06-18

申请号：US14635732

申请日：2015-03-02

Applicant: Samsung Display Co., Ltd. ,  Kookmin University Industry Academy Cooperation Foundation

Inventor： Byung Du AHN ,  Ji Hun LIM ,  Jun Hyung LIM ,  Dae Hwan KIM ,  Jae Hyeong KIM ,  Je Hun LEE ,  Hyun Kwang JUNG

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78606 ,  H01L21/28 ,  H01L27/124 ,  H01L29/786 ,  H01L29/78678 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin film transistor display panel a includes a transparent substrate; a gate electrode positioned on the substrate; a gate insulating layer positioned on the gate electrode; a semiconductor layer positioned on the gate insulating layer and including a channel region; a source electrode and a drain electrode positioned on the semiconductor layer and facing each other; and a passivation layer configured to cover the source electrode, the drain electrode, and the semiconductor layer, wherein the semiconductor layer includes a relatively thick first portion between the source electrode and the gate electrode and a relatively thinner second portion between the drain electrode and the gate electrode overlap, the relatively thick first portion being sufficiently thick to substantially reduce a charge trapping phenomenon that may otherwise occur at a gate electrode to gate dielectric interface if the first portion were as thin as the second portion.

Abstract translation: 薄膜晶体管显示面板a包括透明基板; 位于所述基板上的栅电极; 位于所述栅电极上的栅极绝缘层; 位于所述栅绝缘层上并包括沟道区的半导体层; 位于半导体层上且彼此面对的源电极和漏电极; 以及钝化层，被配置为覆盖所述源电极，所述漏电极和所述半导体层，其中所述半导体层包括在所述源电极和所述栅电极之间的相对较厚的第一部分，以及在所述漏电极和所述半导体层之间的相对较薄的第二部分 栅电极重叠，相对较厚的第一部分足够厚，以便如果第一部分与第二部分一样薄，则基本上可以减少否则可能在栅极电极到栅介质界面处发生的电荷捕获现象。

公开(公告)号：US20220068379A1

公开(公告)日：2022-03-03

申请号：US17405174

申请日：2021-08-18

Applicant: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION

Inventor： Donguk KIM ,  Jun Tae JANG ,  Dae Hwan KIM ,  Dong Myoung KIM ,  Sung Jin CHOI

IPC: G11C13/00 ,  H01L27/24

Abstract: The present invention relates to a synapse and synaptic array, and a computing system using the same. The synaptic device according to an exemplary embodiment of the present invention includes a transistor in which a synaptic input signal is applied to any one electrode of source and drain electrodes; and a plurality of two-terminal variable resistance memory devices in which a first electrode is electrically globally connected to a gate electrode of the transistor, wherein a separate memory voltage is applied to a second electrode of each variable resistance memory device to adjust a gate voltage applied to the gate electrode, thereby controlling a synaptic output signal which is output to the other one of the source and drain electrodes.

公开(公告)号：US20240379156A1

公开(公告)日：2024-11-14

申请号：US18564258

申请日：2022-04-07

Applicant: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION

Inventor： Dae Hwan KIM ,  Dong Myoung KIM ,  Sung Jin CHOI ,  Chang Wook KIM ,  Jin Gyu PARK ,  Dong Uk KIM ,  Hyun Kyu LEE ,  Tae Jun YANG

IPC: G11C13/00 ,  G06N3/063 ,  G06N3/067 ,  G11C13/04 ,  H10B63/00 ,  H10N70/00 ,  H10N70/20

Abstract: The present invention relates to an optical property storage device and a system using the same. The device according to an exemplary embodiment of the present invention comprises: a light transistor in which the conductance between a source electrode and a drain electrode changes in accordance with optical properties of color temperature and illumination of incident light; and a variable resistance memory device of a second terminal in which a first electrode is electrically connected to any one electrode from among the source and drain electrodes of the light transistor, and which stores a conductance changing in accordance with the changed conductance of the light transistor.

公开(公告)号：US20140084293A1

公开(公告)日：2014-03-27

申请号：US13798811

申请日：2013-03-13

Applicant: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION ,  SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du AHN ,  Jung Hwa KIM ,  Ji Hun LIM ,  Je Hun LEE ,  Dae Hwan KIM ,  Hyun Kwang JUNG

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78693 ,  H01L33/387

Abstract: A thin film transistor array panel includes a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a source electrode and a drain electrode on the semiconductor layer and facing each other, a floating metal layer between the source electrode and the drain electrode, and a passivation layer covering the source electrode, the drain electrode, and the floating metal layer. The floating metal layer is electrically floating.

Abstract translation: 薄膜晶体管阵列面板包括基板，基板上的栅极电极，栅电极上的栅极绝缘层，栅极绝缘层上的半导体层，半导体层上的源电极和漏电极，并面对彼此 ，源电极和漏电极之间的浮动金属层，以及覆盖源电极，漏电极和浮置金属层的钝化层。 浮动金属层电浮动。