公开(公告)号：US20140010031A1

公开(公告)日：2014-01-09

申请号：US13767598

申请日：2013-02-14

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY ,  SK HYNIX INC.

Inventor： Seok Hwan CHOI ,  Joong Seob YANG ,  Seung Ho CHANG ,  Sang Sik KIM ,  Sang Chul LEE ,  Ho Yeon LEE ,  Jaekyun MOON ,  Jaehyeong NO

IPC: G11C29/04

CPC classification number: G11C29/04 ,  G11C11/16 ,  G11C11/22 ,  G11C13/00 ,  G11C16/00 ,  G11C29/50004 ,  G11C2029/5002

Abstract: A method for estimating channel characteristics of a nonvolatile memory device including a plurality of memory cells includes the steps of: calculating first threshold voltage distributions of the memory cells programmed according to input data, based on the input data and a physical structure of the memory cells; calculating second threshold voltage distributions of the memory cells, based on output data and the physical structure of the memory cells; and analyzing the relation between the first and second threshold voltage distributions, using a mask.

Abstract translation: 一种用于估计包括多个存储单元的非易失性存储器件的通道特性的方法，包括以下步骤：基于输入数据和存储单元的物理结构，计算根据输入数据编程的存储器单元的第一阈值电压分布 ; 基于输出数据和存储器单元的物理结构计算存储器单元的第二阈值电压分布; 以及使用掩模分析第一和第二阈值电压分布之间的关系。

公开(公告)号：US20190139612A1

公开(公告)日：2019-05-09

申请号：US16031552

申请日：2018-07-10

Applicant: SK hynix Inc.

Inventor： Sang Sik KIM

IPC: G11C16/26 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  G11C16/08 ,  G11C16/34

Abstract: Provided herein is a semiconductor memory device exhibiting improved operating speed and a method of operating the semiconductor memory device. The semiconductor memory device may include a memory cell array, a peripheral circuit, and a control logic. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a read operation on the memory cell array. The control logic may control an operation of the peripheral circuit. The control logic may control the peripheral circuit to perform a repair column masking operation on a selected memory block of the plurality of memory blocks, perform a first test operation on first drain select transistors included in the selected memory block, perform the first test operation on second drain select transistors different from the first drain select transistors while a result of the repair column masking operation remains.

公开(公告)号：US20240168653A1

公开(公告)日：2024-05-23

申请号：US18329380

申请日：2023-06-05

Applicant: SK hynix Inc.

Inventor： Sang Sik KIM

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory system including a storage device comprising a plurality of memory blocks comprising a plurality of pages; and a memory controller configured to update and maintain a page address that is included in a weak page table, based on a number of fail bits for each page that has been accessed based on a page address on which a normal read operation has been indicated, and configured to perform a maintenance operation on the storage device every preset cycle based on the weak page table.

公开(公告)号：US20200183614A1

公开(公告)日：2020-06-11

申请号：US16541804

申请日：2019-08-15

Applicant: SK hynix Inc.

Inventor： Sang Sik KIM

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0882

Abstract: A memory controller configured to control a memory device including memory cells includes an input/output buffer configured to store input data provided from a host; a data converter configured to generate program data obtained by converting the input data such that the number of specific data patterns among data patterns to be stored in the memory cells is changed; and an operation controller configured to provide the program data to the memory device. The program data is generated by selectively inverting a plurality of pieces of logical page data included in the input data.

公开(公告)号：US20230031193A1

公开(公告)日：2023-02-02

申请号：US17563895

申请日：2021-12-28

Applicant: SK hynix Inc.

Inventor： Chung Un NA ,  Sang Sik KIM

IPC: G06F3/06

Abstract: A memory system includes a nonvolatile memory device and a controller. The nonvolatile memory device includes a memory block including a plurality of memory cells, a first memory region of memory cells coupled to a first word line and a second memory region of memory cells coupled to a second word line. The controller performs a single level cell (SLC) program operation on the second memory region and perform a fine program operation on the first memory region after a completion of the SLC program operation on the second memory region.

公开(公告)号：US20160232954A1

公开(公告)日：2016-08-11

申请号：US14794244

申请日：2015-07-08

Applicant: SK hynix Inc.

Inventor： Sang Sik KIM

IPC: G11C8/06 ,  G11C8/10 ,  G11C8/12 ,  G11C15/00

CPC classification number: G11C29/50004 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/42

Abstract: A semiconductor device includes: memory blocks including main data storage units and cycling information storage units; a circuit group that performs a wear leveling operation on the memory blocks; and a control circuit that sets a threshold value based on the cycling information, and controls the circuit group so that the wear leveling operation is performed based on the set threshold value.

Abstract translation: 半导体器件包括：包括主数据存储单元和循环信息存储单元的存储块; 对所述存储块执行磨损均衡操作的电路组; 以及控制电路，其基于循环信息设定阈值，并且控制电路组，使得基于设定的阈值进行磨损均衡操作。

公开(公告)号：US20210241834A1

公开(公告)日：2021-08-05

申请号：US17011555

申请日：2020-09-03

Applicant: SK hynix Inc.

Inventor： Sang Sik KIM ,  Dae Sung KIM

IPC: G11C16/16 ,  G11C16/26 ,  G11C11/56

Abstract: A memory system includes a memory device including a plane including a plurality of memory blocks for storing multi-bit data; and a controller configured to detect, when a problem-causing operation is performed on a first memory block among the memory blocks, remaining memory blocks, except the first memory block, in the plane as being in a problem occurrence candidate group, search for a table, when a read command for a second memory block of the problem occurrence candidate group is received, for a read voltage application order corresponding to the second memory block, and control the memory device to perform a read operation on the second memory block by sequentially applying a plurality of read voltages according to the searched read voltage application order, wherein the problem-causing operation is a program operation or an erase operation.