公开(公告)号：US20220180953A1

公开(公告)日：2022-06-09

申请号：US17344264

申请日：2021-06-10

Applicant: SK hynix Inc.

Inventor： Chung Un NA ,  Yang Hyeon KWON

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26

Abstract: A storage device includes: a memory device including a plurality of memory cells configured to store data and a plurality of word lines connected to the plurality of memory cells and a memory controller in communication with the memory device and configured to control the memory device, including controlling the memory device to perform a read operation perform, upon a failure of the read operation on the memory cell, a read retry operation by changing the read voltage based on a history read table, and wherein the memory controller is further configured to update the history read table, upon a success of the read retry operation, based on whether the word line connected to the memory cell is a last programmed word line according to a program order among word lines connected to the group of memory cells.

公开(公告)号：US20220188234A1

公开(公告)日：2022-06-16

申请号：US17358922

申请日：2021-06-25

Applicant: SK hynix Inc.

Inventor： Chung Un NA

IPC: G06F12/0844 ,  G06F12/02

Abstract: A storage device includes: a memory device including a plurality of planes, and a plurality of cache buffers and data buffers; and a memory controller for controlling the memory device to transmit first data and second data from first plane and second plane into the respective first cache buffer and second cache buffer, and control the first cache buffer and the second cache buffer to transmit the first data and the second data to the memory controller. In response to a read request for third data from a host while the first data is transmitting from the first cache buffer to the memory controller, the memory controller transmits a cache read command to the memory device such that the memory device reads the third data after the first data is completely transmitted to the memory controller, before the second data is transmitted from the second cache buffer.

公开(公告)号：US20220156004A1

公开(公告)日：2022-05-19

申请号：US17327310

申请日：2021-05-21

Applicant: SK hynix Inc.

Inventor： Chung Un NA

IPC: G06F3/06

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device includes a memory device configured to include memory cells for storing data and circuitry structured to generate voltage information indicating whether a voltage used for performing an operation on the memory cells is included in a preset voltage range; and a memory controller in communication with the memory device and configured to transmit, to the memory device, a status command requesting for a status response indicating a status of the operation, and control the memory device to change a voltage used for performing the operation based on the status response provided from the memory device and including the voltage information.

公开(公告)号：US20230031193A1

公开(公告)日：2023-02-02

申请号：US17563895

申请日：2021-12-28

Applicant: SK hynix Inc.

Inventor： Chung Un NA ,  Sang Sik KIM

IPC: G06F3/06

Abstract: A memory system includes a nonvolatile memory device and a controller. The nonvolatile memory device includes a memory block including a plurality of memory cells, a first memory region of memory cells coupled to a first word line and a second memory region of memory cells coupled to a second word line. The controller performs a single level cell (SLC) program operation on the second memory region and perform a fine program operation on the first memory region after a completion of the SLC program operation on the second memory region.

公开(公告)号：US20220197560A1

公开(公告)日：2022-06-23

申请号：US17365160

申请日：2021-07-01

Applicant: SK hynix Inc.

Inventor： Chung Un NA

IPC: G06F3/06

Abstract: There are provided a memory controller and a storage device including the same. The memory controller includes: a command storage including a first read command queue and a second read command queue; a command generation controller for storing a first read command generated in response to a read request and a first physical address in the first read command queue; and a command schedule controller for searching for a first physical address group including at least one second physical address including a page number equal to that of the physical address among the physical addresses stored in the first read command queue and the first physical address, in response to a scheduling event signal provided from the command generation controller.

公开(公告)号：US20160322087A1

公开(公告)日：2016-11-03

申请号：US14842358

申请日：2015-09-01

Applicant: SK hynix Inc.

Inventor： Chung Un NA

IPC: G11C7/14

CPC classification number: G11C16/349 ,  G11C7/1045 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C2211/5641

Abstract: A data storage device includes a nonvolatile memory apparatus including a plurality of pages coupled to a single word line; and a controller suitable for accessing the nonvolatile memory apparatus during one of first and second modes, wherein, the second mode is enabled when the nonvolatile memory apparatus has reached a lifetime limit, and wherein the controller stores the same data in both of a source page and a dummy page during the second mode.

Abstract translation: 数据存储装置包括非易失性存储装置，包括耦合到单个字线的多个页面; 以及适于在第一和第二模式之一期间访问非易失性存储装置的控制器，其中当所述非易失性存储装置已经达到寿命极限时，所述第二模式被启用，并且其中所述控制器将同一数据存储在源页面 以及在第二模式期间的虚页。

公开(公告)号：US20220229595A1

公开(公告)日：2022-07-21

申请号：US17358936

申请日：2021-06-25

Applicant: SK hynix Inc.

Inventor： Ji Hoon LEE ,  Chung Un NA

IPC: G06F3/06

Abstract: Provided is a controller which controls a plurality of memory dies. The controller may include: a processor suitable for generating interleaved read commands based on read requests from a host; a memory interface suitable for acquiring the read commands and a host-requested order of the read commands from the processor, controlling page read operations on the plurality of memory dies in response to the read commands, and acquiring data chunks corresponding to read requests from memory dies whose page read operations are completed, according to the host-requested order; and a host interface suitable for providing the host with responses to the read requests according to the order in which the data chunks are acquired.

公开(公告)号：US20220197561A1

公开(公告)日：2022-06-23

申请号：US17365185

申请日：2021-07-01

Applicant: SK hynix Inc.

Inventor： Chung Un NA

IPC: G06F3/06

Abstract: There are provided a memory controller and a storage device including the same. The memory controller includes: a command storage including a first read command queue and a second read command queue; a command generation controller configured to provide an erase command, a suspend command, a resume command, and output a scheduling event signal after the resume command is output; and a command schedule controller configured to: search for a first physical address group, reorder a output sequence of the first read command queue, and provide a command to perform the read command based on the second read command queue.

公开(公告)号：US20220013190A1

公开(公告)日：2022-01-13

申请号：US17149578

申请日：2021-01-14

Applicant: SK hynix Inc.

Inventor： Chung Un NA

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/52

Abstract: A data storage apparatus may include a data storage device including at least one data die to store first data, and at least one parity die to store second data, third data, and a chip-kill parity, where the at least one data die and the at least one parity die are connected to a channel, and controller in communication with the data storage device and configured to receive a write request for the first data and the second data from a host that is in communication with the data storage device through the channel to generate the chip-kill parity from the first data and the second data. The controller is further configured to read the third data from the parity die and provide the third data to the host upon receipt of a read request for the third data from the host while the chip-kill parity is being updated based on the first data.

公开(公告)号：US20230013450A1

公开(公告)日：2023-01-19

申请号：US17945230

申请日：2022-09-15

Applicant: SK hynix Inc.

Inventor： Chung Un NA

IPC: G06F3/06

Abstract: There are provided a memory controller and a storage device including the same. The memory controller includes: a command storage including a first read command queue and a second read command queue; a command generation controller configured to provide an erase command, a suspend command, a resume command, and output a scheduling event signal after the resume command is output; and a command schedule controller configured to: search for a first physical address group, reorder a output sequence of the first read command queue, and provide a command to perform the read command based on the second read command queue.