公开(公告)号：US20170374085A1

公开(公告)日：2017-12-28

申请号：US15263845

申请日：2016-09-13

Applicant: KYLAND TECHNOLOGY CO., LTD.

Inventor： Jinju WEI

IPC: H04L29/06 ,  H04L12/40 ,  H04L12/28

CPC classification number: H04L63/1416 ,  H04L12/2801 ,  H04L12/40013 ,  H04L12/66 ,  H04L61/106 ,  H04L61/2038 ,  H04L63/0876 ,  H04L63/1425 ,  H04L69/08

Abstract: The invention discloses a method for deep data inspection over an industrial internet field broadband bus, the method including: obtaining, by a first node, a message to be transmitted; judging, by the first node, whether a bus device address in the message to be transmitted lies in a preset range of bus device addresses; and if the bus device address lies in the preset range of bus device addresses, then transmitting, by the first node, the message to be transmitted to a processor of the first node. The first node only forwards the message to be transmitted, lying in the preset range of bus device addresses to thereby improve the security of transmitting the message.

公开(公告)号：US20170371832A1

公开(公告)日：2017-12-28

申请号：US15264033

申请日：2016-09-13

Applicant: KYLAND TECHNOLOGY CO.,LTD.

Inventor： Jinju WEI

IPC: G06F13/42 ,  G06F1/12 ,  G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F1/12 ,  G06F13/364 ,  G06F13/404 ,  H04J3/0641 ,  H04J3/0667 ,  H04L12/4035

Abstract: Disclosed is a method for clock synchronization of an industrial internet field broadband bus, wherein the method is applicable to an industrial internet field broadband bus architecture system including a bus controller and at least one bus terminal, the bus controller is connected with the bus terminal over a two-wire data transfer network, and the method includes steps of: electing one of the bus controller and the bus terminal as a best master clock; determining whether an IP address of the device of the best master clock is the same as an IP address of the bus controller; if so, then determining the bus controller as a master device of clock synchronization, and transmitting by the bus controller a synchronization message to the bus terminal for clock synchronization; and otherwise, returning to the step of electing one of the bus controller and the bus terminal as the best master clock.