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    METHOD AND SYSTEM FOR ENCODING AND DECODING LOW-DENSITY-PARITY-CHECK (LDPC) CODES
    6.
    发明申请
    METHOD AND SYSTEM FOR ENCODING AND DECODING LOW-DENSITY-PARITY-CHECK (LDPC) CODES 有权

    公开(公告)号：US20110083052A1

    公开(公告)日：2011-04-07

    申请号：US12573577

    申请日：2009-10-05

    申请人： Chung Ming Lau ,  Wai Man Tam ,  Chi Kong Tse

    发明人： Chung Ming Lau ,  Wai Man Tam ,  Chi Kong Tse

    IPC分类号： H03M13/07 ,  G06F11/10

    CPC分类号： H03M13/116 ,  H03M13/118 ,  H03M13/1185 ,  H03M13/1188 ,  H03M13/6527 ,  H03M13/6544 ,  H04L1/0045 ,  H04L1/0057

    摘要： A method for encoding data, the method comprising: creating m parity bits from k data bits based on a parity-check matrix (40), the parity-check matrix (40) including a data portion (41) and a parity portion (42), the parity portion (42) includes sub-block matrices, each sub-block matrix being any one from the group consisting of: zero matrix, identity matrix and permutation matrix; and forming a codeword containing the k data bits and the created m parity bits; wherein an upper diagonal is defined in the parity portion (42) starting from the first sub-block matrix in the second column extending to the second last sub-block matrix in the last column, and each sub-block matrix on the upper diagonal is an identity matrix or a permutation matrix, and the sub-block matrices (44) above the upper diagonal are zero matrices; each column from the second column to the third last column of the parity portion (42) contains one or more identity matrices or permutation matrices below the upper diagonal (45) and the remaining sub-block matrices in the same column below the upper diagonal (45) are zero matrices; the last three sub-block matrices (P1, P2, P3) in the first column of the parity portion (42) are identity matrices or permutation matrices and at least two of the last three matrices are the same, and the remaining sub-block matrices in the first column of the parity portion (42) are zero matrices; in the second last column of the parity portion (42), the third last sub-block matrix (P4) is equal to the second last sub-block matrix (P5) and the last sub-block matrix (P6) is a zero matrix, or the third last sub-block matrix (P4) is equal to the last sub-block matrix (P6) and the second last sub-block matrix (P5) is a zero matrix; and the last two sub-block matrices (P7) in the last column of the parity portion (42) are the same, and are identity matrices or permutation matrices.

    HIGH THROUGHPUT DECODER ARCHITECTURE FOR LOW-DENSITY PARITY-CHECK CONVOLUTIONAL CODES
    7.
    发明申请
    HIGH THROUGHPUT DECODER ARCHITECTURE FOR LOW-DENSITY PARITY-CHECK CONVOLUTIONAL CODES 有权
    用于低密度奇偶校验调节代码的高速度解码器架构

    公开(公告)号：US20130212450A1

    公开(公告)日：2013-08-15

    申请号：US13371067

    申请日：2012-02-10

    申请人： Chiu Wing SHAM ,  Xu Chen ,  Chung Ming Lau ,  Yue Zhao ,  Wai Man Tam

    发明人： Chiu Wing SHAM ,  Xu Chen ,  Chung Ming Lau ,  Yue Zhao ,  Wai Man Tam

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： H03M13/1137 ,  H03M13/114 ,  H03M13/1154 ,  H03M13/116 ,  H03M13/6502 ,  H03M13/6505 ,  H03M13/6577

    摘要： A Low-Density Parity-Check Convolutional Code (LPDCCC) decoder (10) for partial parallel decoding of low-density parity-check convolutional codes, the decoder comprising: a plurality of pipeline processors (11) to receive channel messages and edge-messages; each processor (11) having: a plurality of block processing units (BPUs) (13), each BPU (13) having a plurality of check node processors (CNPs) (14) to process check nodes that enter into the processor (11) and a plurality of variable node processors (VNPs) (15) to process variable nodes that are about to leave the processor (11); and a plurality of Random Access Memory (RAM) blocks (30) for dynamic message storage of the channel messages and the edge-messages; wherein in each processor (11), the VNPs (15) are directly connected to corresponding RAM blocks (30), and the CNPs (14) are directly connected to corresponding RAM blocks (30) such that the connections from the VNPs (15) and CNPs (14) to the corresponding RAM blocks (30) are pre-defined and fixed according to a parity-check matrix of an unterminated time-varying periodic LDPCCC.

    摘要翻译： 一种用于低密度奇偶校验卷积码的部分并行解码的低密度奇偶校验卷积码（LPDCCC）解码器（10），所述解码器包括：多个流水线处理器（11），用于接收信道消息和边缘消息 ; 每个处理器（11）具有：多个块处理单元（BPU）（13），每个BPU（13）具有多个校验节点处理器（CNP）（14），用于处理进入处理器（11）的校验节点， 以及多个可变节点处理器（VNP）（15），用于处理即将离开处理器（11）的变量节点; 和用于信道消息和边缘消息的动态消息存储的多个随机存取存储器（RAM）块（30）; 其中在每个处理器（11）中，VNP（15）直接连接到对应的RAM块（30），并且CNP（14）直接连接到对应的RAM块（30），使得来自VNP（15）的连接 并且根据未终止的时变周期性LDPCCC的奇偶校验矩阵来预定义和固定到对应的RAM块（30）的CNP（14）。