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公开(公告)号：US09165615B2
公开(公告)日：2015-10-20
申请号：US13636515
申请日：2011-03-14
CPC分类号： G11C7/1006 , G11C7/02
摘要： Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links.
摘要翻译： 编码器和解码器电路，用于对一系列代码字进行编码和解码一系列数据字。 数据字包括L个符号。 代码字包括M个符号，其中M大于L.一组紧密耦合的M个链路，用于在每一个码字序列中传送相应的符号。 选择码字使得在一系列码字中的每两个连续码字之间，在M链路的子集上出现从低到高和高到低的相等数量的转换。
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公开(公告)号：US09071481B2
公开(公告)日：2015-06-30
申请号：US14342367
申请日：2012-08-10
CPC分类号： H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
摘要： A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.
摘要翻译： 校准反馈均衡器以补偿接收信号中的估计符号间干扰和采样设备的偏移。 判定反馈均衡器被配置为使得采样电路的输出信号表示在校准下的输入信号和采样电路的基准之间的比较。 在包括预定图案的通信信道上接收输入信号。 将预定模式与输出信号进行比较，以确定用于配置考虑到偏移和符号间干扰效应两者的采样电路的调整参考。
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3.发明申请Methods and Circuits for Controlling Amplifier Gain Over Process, Voltage, and Temperature 审中-公开控制放大器过程，电压和温度增益的方法和电路公开(公告)号：US20120139638A1
公开(公告)日：2012-06-07
申请号：US13310609
申请日：2011-12-02
申请人： Kambiz Kaviani , Amir Amirkhany , Aliazam Abbasfar
发明人： Kambiz Kaviani , Amir Amirkhany , Aliazam Abbasfar
IPC分类号： H03F3/04
CPC分类号： H03F3/45183 , H03F3/45197 , H03F3/45632 , H03F2200/447 , H03F2203/45008 , H03F2203/45048 , H03F2203/45078 , H03F2203/45306 , H03F2203/45488 , H03F2203/45686 , H03G1/0029 , H03G1/007
摘要： A receiver includes an amplifier and a transconductance bias circuit. The amplifier gain is largely determined by transconductance and load impedance. The transconductance bias circuit varies the transconductance in inverse proportion to the load impedance to maintain the gain over process, voltage, and temperature. Differential amplifiers can use separate transconductance bias circuits for each amplifier leg, and the bias circuits can be independently controlled to minimize common-mode gain and voltage offsets.
摘要翻译： 接收器包括放大器和跨导偏置电路。 放大器增益主要取决于跨导和负载阻抗。 跨导偏置电路会将跨导与负载阻抗成反比变化，以保持增益超过过程，电压和温度。 差分放大器可以为每个放大器支路使用单独的跨导偏置电路，并且可以独立控制偏置电路以最小化共模增益和电压偏移。
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公开(公告)号：US20130051162A1
公开(公告)日：2013-02-28
申请号：US13636515
申请日：2011-03-14
IPC分类号： G11C7/22
CPC分类号： G11C7/1006 , G11C7/02
摘要： Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links.
摘要翻译： 编码器和解码器电路，用于对一系列代码字进行编码和解码一系列数据字。 数据字包括L个符号。 代码字包括M个符号，其中M大于L.一组紧密耦合的M个链路，用于在每一个码字序列中传送相应的符号。 选择码字使得在一系列码字中的每两个连续码字之间，在M链路的子集上出现从低到高和高到低的相等数量的转换。
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公开(公告)号：US20140226707A1
公开(公告)日：2014-08-14
申请号：US14342367
申请日：2012-08-10
CPC分类号： H04L25/03057 , H04B1/123 , H04L25/03063 , H04L25/03885
摘要： A decision feedback equalizer is calibrated to compensate for estimated inter-symbol interference in a received signal and offsets of sampling devices. The decision feedback equalizer is configured so that an output signal of a sampling circuit represents a comparison between an input signal and a reference of the sampling circuit under calibration. An input signal is received over a communication channel that includes a predetermined pattern. The predetermined pattern is compared to the output signal to determine an adjusted reference for configuring the sampling circuit that accounts for both offset and inter-symbol interference effects.
摘要翻译： 校准反馈均衡器以补偿接收信号中的估计符号间干扰和采样设备的偏移。 判定反馈均衡器被配置为使得采样电路的输出信号表示在校准下的输入信号和采样电路的基准之间的比较。 在包括预定图案的通信信道上接收输入信号。 将预定模式与输出信号进行比较，以确定用于配置考虑到偏移和符号间干扰效应两者的采样电路的调整参考。
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公开(公告)号：US20130063191A1
公开(公告)日：2013-03-14
申请号：US13612540
申请日：2012-09-12
申请人： Dinesh Patil , Mohammad Hekmat , Kambiz Kaviani , Amir Amirkhany
发明人： Dinesh Patil , Mohammad Hekmat , Kambiz Kaviani , Amir Amirkhany
CPC分类号： H03L7/0812 , H03K5/1565
摘要： A duty-cycle correction circuit calibrates the duty cycle of a periodic input signal. The correction circuit includes a state machine that samples the input signal using a sample signal of a sample period. The sample period is selected to scan a period of the input signal over a number of sample periods. The resultant difference between the number of high and low samples provides a measure of the duty cycle deviation from e.g. 50%. An adjustable delay circuit adjusts the relative timing of the rising and falling edges of the input signal, and thus the duty cycle, responsive to the measure of duty cycle.
摘要翻译： 占空比校正电路校准周期性输入信号的占空比。 校正电路包括使用采样周期的采样信号对输入信号进行采样的状态机。 选择采样周期以在多个采样周期上扫描输入信号的周期。 所得到的高和低样本数之间的差异提供了与例如数据的占空比偏差的度量。 50％。 可调节延迟电路调整输入信号的上升沿和下降沿的相对定时，从而根据占空比的测量来调整占空比。
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公开(公告)号：US08531206B2
公开(公告)日：2013-09-10
申请号：US13391383
申请日：2010-09-14
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K19/017581 , H03M1/1061 , H03M1/745 , H04L25/0278 , H04L25/0288 , H04L25/03343
摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.
摘要翻译： 具有相对较少数量的子驱动器分支或切片的高分辨率输出驱动器，每个子驱动器分支或切片具有显着大于量化步长的标称阻抗，并且通过显着小于量化步长的阻抗步长递增地彼此不同。 在一个实现中，这种“差分”或“不均匀”子驱动器切片实现n选择k均衡器的相应元件，每个这样的差分子驱动器切片由均匀元件阻抗校准DAC实现。 在另一实施方式中，均匀分片均衡器的每个分量由差分片阻抗校准DAC实现，并且在又一实现中，差分片均衡器的每个分量由差分片阻抗校准DAC实现。 在一组额外的实施方案中，均衡和阻抗校准功能在各个并行的驱动器分支组中实现，而不是分层实现中嵌套的“DAC内的DAC”布置。 通过这种双边安排，避免了均衡器和校准器量化的乘法，从而降低了满足指定范围和分辨率所需的副驱动器片的总数。
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公开(公告)号：US20120147944A1
公开(公告)日：2012-06-14
申请号：US13391383
申请日：2010-09-14
IPC分类号： H04L27/01
CPC分类号： H03K19/0005 , H03K19/017581 , H03M1/1061 , H03M1/745 , H04L25/0278 , H04L25/0288 , H04L25/03343
摘要： High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.
摘要翻译： 具有相对较少数量的子驱动器分支或切片的高分辨率输出驱动器，每个子驱动器分支或切片具有显着大于量化步长的标称阻抗，并且通过显着小于量化步长的阻抗步长递增地彼此不同。 在一个实现中，这种“差分”或“不均匀”子驱动器切片实现n选择k均衡器的相应元件，每个这样的差分子驱动器切片由均匀元件阻抗校准DAC实现。 在另一实施方式中，均匀分片均衡器的每个分量由差分片阻抗校准DAC实现，并且在又一实现中，差分片均衡器的每个分量由差分片阻抗校准DAC实现。 在一组额外的实施方案中，均衡和阻抗校准功能在各个并行的驱动器分支组中实现，而不是分层实现中嵌套的“DAC内的DAC”布置。 通过这种双边安排，避免了均衡器和校准器量化的乘法，从而降低了满足指定范围和分辨率所需的副驱动器片的总数。
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公开(公告)号：US09035677B2
公开(公告)日：2015-05-19
申请号：US14130756
申请日：2012-06-11
IPC分类号： H03K19/0175 , H04L25/02 , H04L25/03
CPC分类号： H03K19/017509 , H04L25/0274 , H04L25/0282 , H04L25/0294 , H04L25/03146 , H04L25/03878
摘要： A transceiver includes a transmitter and receiver that form a series current path between two power-supply nodes. Powering both the transmitter and receiver with the same supply current saves power. The transmitter functions as a resistive load for the receiver, and thus performs useful work with power that would otherwise be dissipated as waste heat.
摘要翻译： 收发器包括在两个电源节点之间形成串联电流路径的发射器和接收器。 以相同的电源电流为发射机和接收机供电节省电力。 发射器作为接收器的电阻负载起作用，因此可以用功率进行有用的工作，否则这些功率将作为废热消散。
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公开(公告)号：US08817863B2
公开(公告)日：2014-08-26
申请号：US13357736
申请日：2012-01-25
IPC分类号： H03H7/30
CPC分类号： H04L25/03885
摘要： The disclosed embodiments relate to the design of a linear equalizer that supports low-power, high-speed data transfers. In some embodiments, this linear equalizer contains a passive network that provides selective frequency peaking in a frequency range associated with a falling edge of a frequency response of the channel. It also includes a level shifter coupled between the channel and the passive network, wherein the level shifter is an active component that provides amplification and/or level-shifting. Moreover, the linear equalizer is designed so that power from the level shifter facilitates the selective frequency peaking of the passive network.
摘要翻译： 所公开的实施例涉及支持低功率，高速数据传输的线性均衡器的设计。 在一些实施例中，该线性均衡器包含无源网络，其在与频道的频率响应的下降沿相关联的频率范围内提供选择性频率峰化。 它还包括耦合在通道和无源网络之间的电平移位器，其中电平移位器是提供放大和/或电平转换的有源部件。 此外，线性均衡器被设计成使得来自电平移位器的功率有助于无源网络的选择性频率峰化。
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