摘要:
High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.
摘要:
High resolution output drivers having a relatively small number of sub-driver branches or slices each having nominal impedances substantially larger than a quantization step and that incrementally differ from one another by an impedance step substantially smaller than a quantization step. In one implementation, such “differential” or “non-uniform” sub-driver slices implement respective elements of an n choose k equalizer, with each such differential sub-driver slice being implemented by a uniform-element impedance calibration DAC. In another implementation, each component of a uniform-slice equalizer is implemented by a differential-slice impedance calibration DAC, and in yet another implementation, each component of a differential-slice equalizer is implemented by a differential-slice impedance calibration DAC. In an additional set of implementations, equalization and impedance calibration functions are implemented bilaterally in respective parallel sets of driver branches, rather than in the nested “DAC within a DAC” arrangement of the hierarchical implementations. Through such bilateral arrangement, multiplication of the equalizer and calibrator quantizations is avoided, thereby lowering the total number of sub-driver slices required to meet the specified ranges and resolutions.
摘要:
Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different termination schemes to save die area.
摘要:
An integrated circuit supports multiple communication modes using different input/output (IO) voltages. The IC includes a low-voltage communication circuit operating at a low IO voltage in a low-voltage mode, and a high-voltage communication circuit operating at a high IO voltage in a high-voltage mode. The low-voltage communication circuit includes low-voltage transistors in a critical path that exhibits sensitivity to a destructive voltage less than the high IO voltage. The low-voltage communication circuit is therefore provided with protection circuitry to protect the low-voltage transistors from the high 10 voltage.
摘要:
An integrated circuit supports multiple communication modes using different input/output (IO) voltages. The IC includes a low-voltage communication circuit operating at a low IO voltage in a low-voltage mode, and a high-voltage communication circuit operating at a high IO voltage in a high-voltage mode. The low-voltage communication circuit includes low-voltage transistors in a critical path that exhibits sensitivity to a destructive voltage less than the high IO voltage. The low-voltage communication circuit is therefore provided with protection circuitry to protect the low-voltage transistors from the high 10 voltage.
摘要:
Disclosed are methods and circuits that support different on-die termination (ODT) schemes for a plurality of signaling schemes using a relatively small number of external calibration pads. These methods and circuits develop control signals for calibrating any of multiple termination schemes that might be used by associated communication circuits. The ODT control circuits, entirely or predominantly instantiated on-die, share circuit resources employed in support of the different termination schemes to save die area.
摘要:
A geometric DAC architecture includes a series of substantially identical sub-DACs, each sub-DAC having n taps. The sub-DACs are fed from a bias-DAC having m=(total number of taps needed)/n taps. The output of each of the m taps is increased geometrically at a rate of kn. The geometric DAC architecture control lines desirably require only (m+n) taps compared with (m×n) taps for the simpler more conventional approach. Further, the geometric DAC architecture requires less real estate than the simpler more conventional approach, is easy to expand because it is modular, and generates an output current that is always monotonic, regardless of errors in transistor sizes and PVT variations. The n tap control lines are coded by alternately inverting n control line inputs between sub-DACs such that any state transition associated with the geometric DAC occurs with only one bit change in each of the control lines.
摘要:
Transmit parallel interfaces and methods are provided in which a clock signal is generated that maximizes the setup and hold window of input data. In at least some embodiments, a divider circuit provides a clock signal in one clock domain that has a rising edge located very close to the falling edge of a system clock in another clock domain.
摘要:
A method and apparatus generates output clock pulses, having leading and trailing edges that are adjusted in a pulse forming processor, according to the relative phase of an output clock and output data. Dynamic adjustment of the leading and trailing edges of output clock pulses improves the performance of high-speed devices significantly.
摘要:
An apparatus and method for producing dummy data is based on timing paths co-located with the address/data paths of the memory. An output clock generator uses the dummy data. The technique for producing dummy data is particularly important for memory systems in which the output of memory cells do not normally provide large voltage swings, making them less practical for self timing approaches to dummy data generation.