公开(公告)号：US08674444B2

公开(公告)日：2014-03-18

申请号：US13422297

申请日：2012-03-16

申请人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

发明人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

IPC分类号： H01L27/12

CPC分类号： H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

摘要： A semiconductor structure includes a semiconductor substrate. A conductive gate abuts a gate insulator for controlling conduction of a channel region. The gate insulator abuts the channel region. A source region and a drain region are associated with the conductive gate. The source region includes a first material and the drain region includes a second material. The conductive gate is self-aligned to the first and the second material.

摘要翻译： 半导体结构包括半导体衬底。 导电栅极邻接栅极绝缘体，用于控制沟道区的导通。 栅极绝缘体邻接沟道区域。 源极区域和漏极区域与导电栅极相关联。 源极区域包括第一材料，漏极区域包括第二材料。 导电栅极与第一和第二材料自对准。

公开(公告)号：US08461625B2

公开(公告)日：2013-06-11

申请号：US13080352

申请日：2011-04-05

申请人： Kangguo Cheng ,  Haining S. Yang

发明人： Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L29/78

CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L29/7845 ,  Y10S438/926

摘要： An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.

摘要翻译： 提供了具有应力增强通道的集成电路，设计结构和制造集成电路的方法。 该方法包括在衬底上形成虚拟栅极结构并在虚拟栅极结构中形成沟槽。 该方法还包括用应变诱导材料填充沟槽的一部分并用栅极材料填充沟槽的剩余部分。

公开(公告)号：US20120235236A1

公开(公告)日：2012-09-20

申请号：US13422297

申请日：2012-03-16

申请人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

发明人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

摘要： A semiconductor structure includes a semiconductor substrate. A conductive gate abuts a gate insulator for controlling conduction of a channel region. The gate insulator abuts the channel region. A source region and a drain region are associated with the conductive gate. The source region includes a first material and the drain region includes a second material. The conductive gate is self-aligned to the first and the second material.

摘要翻译： 半导体结构包括半导体衬底。 导电栅极邻接栅极绝缘体，用于控制沟道区的导通。 栅极绝缘体邻接沟道区域。 源极区域和漏极区域与导电栅极相关联。 源极区域包括第一材料，漏极区域包括第二材料。 导电栅极与第一和第二材料自对准。

公开(公告)号：US08232210B2

公开(公告)日：2012-07-31

申请号：US12562222

申请日：2009-09-18

申请人： Kangguo Cheng ,  Haining S. Yang

发明人： Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L21/311

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/265 ,  H01L21/28008 ,  H01L21/32139 ,  H01L21/76816

摘要： A method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features.

摘要翻译： 形成集成电路（IC）器件特征的方法包括：在待图案化的半导体器件层上形成初始基本平坦的硬掩模层; 在所述硬掩模层上形成第一光致抗蚀剂层; 图案化第一光致抗蚀剂层中的第一组半导体器件特征; 在硬掩模层中以保持硬掩模层基本上平面的方式对准第一组半导体器件特征; 去除第一光致抗蚀剂层; 在所述基本上平坦的硬掩模层上形成第二光致抗蚀剂层; 在第二光致抗蚀剂层中图形化第二组半导体器件特征; 在硬掩模层中以保持硬掩模层基本上平面的方式对准第二组半导体器件特征; 去除所述第二光致抗蚀剂层; 以及通过移除与所述第一和第二组半导体器件特征对应的部分来在所述硬掩模层内产生形貌。

公开(公告)号：US20100176450A1

公开(公告)日：2010-07-15

申请号：US12351263

申请日：2009-01-09

申请人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

发明人： Haining S. Yang ,  Kangguo Cheng ,  Robert Wong

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

摘要： A semiconductor structure is described. The structure includes a semiconductor substrate having a conductive gate abutting a gate insulator for controlling conduction of a channel region; and a source region and a drain region associated with the conductive gate, where the source region includes a first material and the drain region includes a second material, and where the conductive gate is self-aligned to the first material and the second material. In one embodiment, the first material includes Si and the second material includes SiGe. A method of forming a semiconductor structure is also described. The method includes forming a pad layer on a top surface of a SOI layer of a semiconductor substrate; patterning the pad layer and a portion of the SOI layer for forming a SiGe layer; epitaxially growing the SOI layer for forming a Si layer and a SiGe layer adjacent to a sidewall of the SOI layer; selectively pulling a portion of the pad layer; forming a gate dielectric of a portion of the SiGe layer and the SOI layer; forming a gate conductor over the gate dielectric; removing the remaining of the pad layer; forming a source region in at least one of the SOI layer and the SiGe layer; and forming a drain region in at least one of the SOI layer and the SiGe layer.

摘要翻译： 描述半导体结构。 该结构包括具有邻接栅极绝缘体的导电栅极以控制沟道区域的导通的半导体衬底; 以及与导电栅极相关联的源极区域和漏极区域，其中源极区域包括第一材料，并且漏极区域包括第二材料，并且其中导电栅极与第一材料和第二材料自对准。 在一个实施例中，第一材料包括Si，第二材料包括SiGe。 还描述了形成半导体结构的方法。 该方法包括在半导体衬底的SOI层的顶表面上形成焊盘层; 图案化衬垫层和用于形成SiGe层的SOI层的一部分; 外延生长用于形成Si层的SOI层和与SOI层的侧壁相邻的SiGe层; 选择性地拉动衬垫层的一部分; 形成SiGe层和SOI层的一部分的栅极电介质; 在所述栅极电介质上形成栅极导体; 去除衬垫层的剩余部分; 在所述SOI层和所述SiGe层中的至少一个中形成源区; 以及在所述SOI层和所述SiGe层中的至少一个中形成漏区。

公开(公告)号：US20100038705A1

公开(公告)日：2010-02-18

申请号：US12190109

申请日：2008-08-12

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Haining S. Yang

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66545 ,  H01L21/28026 ,  H01L21/28194 ,  H01L29/512 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide an undercut beneath a spacer that is adjacent a gate electrode within a field effect structure such as a field effect transistor structure. The undercut, which may completely or incompletely encompass the area interposed between the spacer and a semiconductor substrate is filled with a gate dielectric. The gate dielectric has a greater thickness interposed between the spacer and the semiconductor substrate than the gate and the semiconductor substrate. The semiconductor structure may be fabricated using a sequential replacement gate dielectric and gate electrode method.

摘要翻译： 半导体结构和用于制造半导体结构的方法在诸如场效应晶体管结构的场效应结构内的与栅电极相邻的间隔物之下提供底切。 可以完全或不完全地覆盖插入在间隔物和半导体衬底之间的区域的底切部被栅极电介质填充。 与栅极和半导体衬底相比，栅极电介质具有比间隔物和半导体衬底之间更大的厚度。 可以使用顺序替换栅极电介质和栅极电极法制造半导体结构。

公开(公告)号：US08765558B2

公开(公告)日：2014-07-01

申请号：US13427237

申请日：2012-03-22

申请人： Kangguo Cheng ,  Haining S. Yang

发明人： Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L21/02

CPC分类号： H01L21/823878 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203

摘要： A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.

公开(公告)号：US08629506B2

公开(公告)日：2014-01-14

申请号：US12407011

申请日：2009-03-19

申请人： Kangguo Cheng ,  Haining S. Yang

发明人： Kangguo Cheng ,  Haining S. Yang

IPC分类号： H01L21/70

CPC分类号： H01L21/823878 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203

摘要： A CMOS structure and a method for fabricating the CMOS structure include within a semiconductor substrate a first gate located over a first active region of a first polarity and a second gate located over a second active region of a second polarity different than the first polarity. The first active region and the second active region are separated by an isolation region. The first gate and the second gate are co-linear, with facing endwalls that terminate over the isolation region. The facing endwalls do not have a spacer located or formed adjacent or adjoining thereto, although sidewalls of the first gate and the second gate do. The CMOS structure may be fabricated using a sequential replacement gate method.

摘要翻译： CMOS结构和用于制造CMOS结构的方法包括位于半导体衬底内的位于第一极性的第一有源区上的第一栅极和位于不同于第一极性的第二极性的第二有源区上的第二栅极。 第一有源区和第二有源区被隔离区隔开。 第一栅极和第二栅极是共线的，面向端壁终止在隔离区上。 面对的端壁不具有相邻或邻接的间隔件，尽管第一栅极和第二栅极的侧壁都是。 可以使用顺序替换栅极方法来制造CMOS结构。

公开(公告)号：US20090302412A1

公开(公告)日：2009-12-10

申请号：US12132887

申请日：2008-06-04

申请人： KANGGUO CHENG ,  Haining S. Yang

发明人： KANGGUO CHENG ,  Haining S. Yang

IPC分类号： H01L29/00 ,  H01L21/76 ,  G06F9/45

CPC分类号： H01L21/823828 ,  H01L21/823807 ,  H01L29/7845 ,  Y10S438/926

摘要： An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material.

摘要翻译： 提供了具有应力增强通道的集成电路，设计结构和制造集成电路的方法。 该方法包括在衬底上形成虚拟栅极结构并在虚拟栅极结构中形成沟槽。 该方法还包括用应变诱导材料填充沟槽的一部分并用栅极材料填充沟槽的剩余部分。

公开(公告)号：US20090108356A1

公开(公告)日：2009-04-30

申请号：US11924053

申请日：2007-10-25

申请人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

发明人： Kangguo Cheng ,  Michael P. Chudzik ,  Rama Divakaruni ,  Geng Wang ,  Robert C. Wong ,  Haining S. Yang

IPC分类号： H01L29/78 ,  H01L21/44

CPC分类号： H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： A metal gate stack containing a metal layer having a mid-band-gap work function is formed on a high-k gate dielectric layer. A threshold voltage adjustment oxide layer is formed over a portion of the high-k gate dielectric layer to provide devices having a work function near a first band gap edge, while another portion of the high-k dielectric layer remains free of the threshold voltage adjustment oxide layer. A gate stack containing a semiconductor oxide based gate dielectric and a doped polycrystalline semiconductor material may also be formed to provide a gate stack having a yet another work function located near a second band gap edge which is the opposite of the first band gap edge. A dense circuit containing transistors of p-type and n-type with the mid-band-gap work function are formed in the region containing the threshold voltage adjustment oxide layer.

摘要翻译： 在高k栅极电介质层上形成包含具有中带隙功函数的金属层的金属栅极堆叠。 在高k栅介质层的一部分上形成阈值电压调整氧化物层，以提供在第一带隙边缘附近具有功函数的器件，而高k电介质层的另一部分保持没有阈值电压调整 氧化层。 还可以形成包含半导体氧化物基栅极电介质和掺杂多晶半导体材料的栅极堆叠，以提供具有位于与第一带隙边缘相反的第二带隙边缘附近的又一功能功能的栅极堆叠。 在包含阈值电压调整氧化物层的区域中形成包含具有中带功函数的p型和n型晶体管的密集电路。