公开(公告)号：US09514258B2

公开(公告)日：2016-12-06

申请号：US13531189

申请日：2012-06-22

申请人： Karen Amirkhanyan ,  Karen Darbinyan ,  Arman Davtyan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

发明人： Karen Amirkhanyan ,  Karen Darbinyan ,  Arman Davtyan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/14

摘要： A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.

摘要翻译： 存储器结构模型以有效的方式直接从存储器配置信息和存储器布局信息生成。 通过分析存储器的配置信息和相应的存储器布局来生成带分布的信息。 通过使用物理位模式对存储器布局进行编程，提取对应的逻辑位模式，然后分析物理位模式与逻辑位模式之间的差异来产生关于存储器布局中地址加扰的信息。 带分布信息和地址扰乱信息被组合到用于设计有效的测试和修复引擎的存储器结构模型中。

公开(公告)号：US20130346056A1

公开(公告)日：2013-12-26

申请号：US13531189

申请日：2012-06-22

申请人： Karen Amirkhanyan ,  Karen Darbinyan ,  Arman Davtyan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

发明人： Karen Amirkhanyan ,  Karen Darbinyan ,  Arman Davtyan ,  Gurgen Harutyunyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/14

摘要： A memory structural model is generated directly from memory configuration information and memory layout information in an efficient manner. Information on strap distribution is generated by analyzing configuration information of the memory and the corresponding memory layout. Information on scrambling of addresses in the memory layout is generated by programming the memory layout with physical bit patterns, extracting corresponding logical bit patterns and then analyzing the discrepancy between the physical bit patterns and the logical bit patterns. The strap distribution information and the address scrambling information are combined into the memory structural model used for designing an efficient test and repair engine.

摘要翻译： 存储器结构模型以有效的方式直接从存储器配置信息和存储器布局信息生成。 通过分析存储器的配置信息和相应的存储器布局来生成带分布的信息。 通过使用物理位模式对存储器布局进行编程，提取对应的逻辑位模式，然后分析物理位模式与逻辑位模式之间的差异来产生关于存储器布局中地址加扰的信息。 带分布信息和地址扰乱信息被组合到用于设计有效的测试和修复引擎的存储器结构模型中。

公开(公告)号：US08850277B2

公开(公告)日：2014-09-30

申请号：US13183471

申请日：2011-07-15

申请人： Karen Amirkhanyan ,  Hayk Grigoryan ,  Gurgen Harutyunyan ,  Tatevik Melkumyan ,  Samvel Shoukourian ,  Alex Shubat ,  Valery Vardanian ,  Yervant Zorian

发明人： Karen Amirkhanyan ,  Hayk Grigoryan ,  Gurgen Harutyunyan ,  Tatevik Melkumyan ,  Samvel Shoukourian ,  Alex Shubat ,  Valery Vardanian ,  Yervant Zorian

IPC分类号： G11C29/00 ,  G11C29/08 ,  G11C29/10 ,  G11C11/41

CPC分类号： G11C29/08 ,  G11C11/41 ,  G11C29/10

摘要： A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.

摘要翻译： 一种用于测试电子存储器的方法和系统。 该方法包括使电子存储器经受预定的一组测试条件的第一测试条件。 该方法还包括使用预定的测试算法对于第一测试条件首次多次测试电子存储器的功能。 该方法还包括如果电子存储器的功能是令人满意的，则从预定的测试条件组检查第二测试条件的可用性。 此外，该方法包括如果第二测试条件可用，则使用预定测试算法来测试第二测试条件的电子存储器的功能，第二多次。 此外，如果电子存储器的功能令人满意，则该方法包括接受用于产品的电子存储器。

公开(公告)号：US08112730B2

公开(公告)日：2012-02-07

申请号：US12249085

申请日：2008-10-10

申请人： Karen Aleksanyan ,  Karen Amirkhanyan ,  Sergey Karapetyan ,  Alexander Shubat ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

发明人： Karen Aleksanyan ,  Karen Amirkhanyan ,  Sergey Karapetyan ,  Alexander Shubat ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G01R31/318357 ,  G01R31/3187 ,  G06F17/5022 ,  G11C29/54

摘要： A structural primitive verification tool for memory compilers is described. A first set of memory structural primitives are supplied by a designer by filling in fields of a presented user interface. The first set of structural primitives describe certain physical layout features of a proposed memory array in an integrated circuit. A first model of a memory instance derived from the first set of memory structural primitives supplied by the designer is compared to a second model of a memory instance derived from a memory layout file from a memory compiler under-test. The first model is verified against the second model to verify to an integrity of the first set of memory structural primitives supplied by the designer compared to the memory layout file derived from a second set of memory structural primitives configuring that memory instance from the memory compiler.

摘要翻译： 描述了用于存储器编译器的结构原始验证工具。 第一组存储器结构图元由设计者通过填充呈现的用户界面的字段来提供。 第一组结构图元描述了集成电路中所提出的存储器阵列的某些物理布局特征。 将由设计者提供的第一组存储器结构基元派生的存储器实例的第一模型与来自存储器编译器未测试的存储器布局文件的存储器实例的第二模型进行比较。 针对第二模型验证第一模型以验证设计者提供的第一组存储器结构原语的完整性，与从存储器编译器配置该存储器实例的第二组存储器结构基元派生的存储器布局文件相比较。

公开(公告)号：US20090106716A1

公开(公告)日：2009-04-23

申请号：US12249085

申请日：2008-10-10

申请人： Karen Aleksanyan ,  Karen Amirkhanyan ,  Sergey Karapetyan ,  Alexander Shubat ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

发明人： Karen Aleksanyan ,  Karen Amirkhanyan ,  Sergey Karapetyan ,  Alexander Shubat ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

IPC分类号： G06F17/50

CPC分类号： G01R31/318357 ,  G01R31/3187 ,  G06F17/5022 ,  G11C29/54

摘要： A structural primitive verification tool for memory compilers is described. A first set of memory structural primitives are supplied by a designer by filling in fields of a presented user interface. The first set of structural primitives describe certain physical layout features of a proposed memory array in an integrated circuit. A first model of a memory instance derived from the first set of memory structural primitives supplied by the designer is compared to a second model of a memory instance derived from a memory layout file from a memory compiler under-test. The first model is verified against the second model to verify to an integrity of the first set of memory structural primitives supplied by the designer compared to the memory layout file derived from a second set of memory structural primitives configuring that memory instance from the memory compiler.

摘要翻译： 描述了用于存储器编译器的结构原始验证工具。 第一组存储器结构图元由设计者通过填充呈现的用户界面的字段来提供。 第一组结构图元描述了集成电路中所提出的存储器阵列的某些物理布局特征。 将由设计者提供的第一组存储器结构基元派生的存储器实例的第一模型与来自存储器编译器未测试的存储器布局文件的存储器实例的第二模型进行比较。 针对第二模型验证第一模型以验证设计者提供的第一组存储器结构基元的完整性，与从存储器编译器配置该存储器实例的第二组存储器结构基元派生的存储器布局文件相比较。

公开(公告)号：US07768840B1

公开(公告)日：2010-08-03

申请号：US11847047

申请日：2007-08-29

申请人： Karen Aleksanyan ,  Karen Amirkhanyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

发明人： Karen Aleksanyan ,  Karen Amirkhanyan ,  Samvel Shoukourian ,  Valery Vardanian ,  Yervant Zorian

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/1012

摘要： A computer-implemented method for creating an integrated circuit, IC, test engine for testing a proposed IC memory array using new memory structural model. An IC designer inputs the number of words that can be stored and a column multiplexer ratio in a proposed IC memory array. A selection of one or more procedures is made from a library of computer-readable procedures. Each of the procedures is to produce one or more structural primitives that describe certain physical layout features of the proposed IC memory array, without analyzing a CAD layout file of the proposed IC memory array. The library of procedures as a whole translates between a physical model of a family of IC memory arrays and a user interface model of the family. A data background, DB, pattern is produced to be used by the test engine in testing the proposed IC memory array. This is done by executing the selected one or more procedures, wherein these procedures take as input the received number of words and column multiplexer size. Other embodiments are also described.

摘要翻译： 一种用于创建用于使用新的存储器结构模型测试所提出的IC存储器阵列的集成电路IC测试引擎的计算机实现的方法。 IC设计人员在提出的IC存储器阵列中输入可存储的字数和列多路复用器比。 从计算机可读程序库中选择一个或多个过程。 每个过程是产生一个或多个描述所提出的IC存储器阵列的某些物理布局特征的结构图元，而不分析所提出的IC存储器阵列的CAD布局文件。 程序库作为一个整体，转换为IC存储器阵列系列的物理模型和家族的用户界面模型。 在测试所提出的IC存储器阵列时，产生数据背景，DB，模式以供测试引擎使用。 这通过执行所选择的一个或多个过程来完成，其中这些过程将接收到的字数和列多路复用器大小作为输入。 还描述了其它实施例。