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公开(公告)号：US20070252618A1
公开(公告)日：2007-11-01
申请号：US11413315
申请日：2006-04-28
IPC分类号： H03K19/094
CPC分类号： H03K19/0185 , H03K19/09432
摘要： A signal converter circuit including an input circuit and an output circuit. The input circuit is configured to receive current mode logic signals and provide differential input signals based on the current mode logic signals. The output circuit is configured to receive the differential input signals and provide rail-to-rail output signals based on the differential input signals. The output circuit is configured to switch the rail-to-rail output signals in response to a common edge type in each of the differential input signals.
摘要翻译： 一种包括输入电路和输出电路的信号转换器电路。 输入电路被配置为接收电流模式逻辑信号并且基于当前模式逻辑信号提供差分输入信号。 输出电路被配置为接收差分输入信号并且基于差分输入信号提供轨到轨输出信号。 输出电路被配置为响应于每个差分输入信号中的公共边缘类型来切换轨到轨输出信号。
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公开(公告)号：US07681063B2
公开(公告)日：2010-03-16
申请号：US11093554
申请日：2005-03-30
CPC分类号： H03L7/107 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/033
摘要： A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the transitions in the data. The second circuit is configured to receive the first signal and provide a first shift signal based on the first signal. The third circuit is configured to receive the first shift signal, wherein the first circuit, the second circuit, and the third circuit are configured to form a first circuit loop and the third circuit is configured to disable the first circuit loop and shift the clock signal based on the first shift signal.
摘要翻译： 时钟数据恢复电路包括第一电路，第二电路和第三电路。 第一电路被配置为接收数据和时钟信号并且检测数据中的转变并且基于时钟信号和数据中的转换来提供第一信号。 第二电路被配置为接收第一信号并且基于第一信号提供第一移位信号。 第三电路被配置为接收第一移位信号，其中第一电路，第二电路和第三电路被配置为形成第一电路回路，并且第三电路被配置为禁用第一电路回路并且移位时钟信号 基于第一移位信号。
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公开(公告)号：US20060227914A1
公开(公告)日：2006-10-12
申请号：US11093554
申请日：2005-03-30
IPC分类号： H04L7/00
CPC分类号： H03L7/107 , H03L7/0814 , H03L7/091 , H03L7/093 , H04L7/033
摘要： A clock data recovery circuit includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive data and a clock signal and to detect transitions in the data and provide a first signal based on the clock signal and the transitions in the data. The second circuit is configured to receive the first signal and provide a first shift signal based on the first signal. The third circuit is configured to receive the first shift signal, wherein the first circuit, the second circuit, and the third circuit are configured to form a first circuit loop and the third circuit is configured to disable the first circuit loop and shift the clock signal based on the first shift signal.
摘要翻译： 时钟数据恢复电路包括第一电路，第二电路和第三电路。 第一电路被配置为接收数据和时钟信号并且检测数据中的转变并且基于时钟信号和数据中的转换来提供第一信号。 第二电路被配置为接收第一信号并且基于第一信号提供第一移位信号。 第三电路被配置为接收第一移位信号，其中第一电路，第二电路和第三电路被配置为形成第一电路回路，并且第三电路被配置为禁用第一电路回路并且移位时钟信号 基于第一移位信号。
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公开(公告)号：US07813289B2
公开(公告)日：2010-10-12
申请号：US11346064
申请日：2006-02-02
IPC分类号： H04L1/00
CPC分类号： G06F13/4072
摘要： An electrical idle detection circuit including a full wave rectifier and a first amplifier. The full wave rectifier is configured to receive differential input signals and provide a rectified output signal based on the differential input signals. The first amplifier is configured to receive a first input signal based on the rectified output signal and a second input signal based on a reference signal. The first amplifier is configured to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.
摘要翻译： 一种包括全波整流器和第一放大器的电怠速检测电路。 全波整流器配置为接收差分输入信号，并根据差分输入信号提供整流输出信号。 第一放大器被配置为基于经整流的输出信号接收第一输入信号，并且基于参考信号接收第二输入信号。 第一放大器被配置为提供输出信号，其基于第一输入信号和第二输入信号来指示差分输入信号是有效和电空闲之一。
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公开(公告)号：US07733815B2
公开(公告)日：2010-06-08
申请号：US11494848
申请日：2006-07-28
CPC分类号： H03M1/1245
摘要： A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.
摘要翻译： 数据采样器，包括第一级和第二级。 第一级被配置为基于差分信号接收差分信号并提供第一输出信号中的第一边沿速率和第二输出信号中的第二边缘速率。 第二级被配置为放大第一输出信号和第二输出信号之间的差以提供再生的输出信号。 第二级基于第一边沿速率和第二边缘速率，提供第一内部信号中的第三边沿速率和第二内部信号中的第四边缘速率。
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公开(公告)号：US20080024215A1
公开(公告)日：2008-01-31
申请号：US11494848
申请日：2006-07-28
IPC分类号： H03F3/04
CPC分类号： H03M1/1245
摘要： A data sampler including a first stage and a second stage. The first stage is configured to receive differential signals and provide a first edge rate in a first output signal and a second edge rate in a second output signal based on the differential signals. The second stage is configured to amplify the difference between the first output signal and the second output signal to provide regenerated output signals. The second stage provides a third edge rate in a first internal signal and a fourth edge rate in a second internal signal based on the first edge rate and the second edge rate.
摘要翻译： 数据采样器，包括第一级和第二级。 第一级被配置为基于差分信号接收差分信号并提供第一输出信号中的第一边沿速率和第二输出信号中的第二边缘速率。 第二级被配置为放大第一输出信号和第二输出信号之间的差以提供再生的输出信号。 第二级基于第一边沿速率和第二边缘速率，提供第一内部信号中的第三边沿速率和第二内部信号中的第四边缘速率。
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公开(公告)号：US20070180281A1
公开(公告)日：2007-08-02
申请号：US11346064
申请日：2006-02-02
IPC分类号： G06F1/32
CPC分类号： G06F13/4072
摘要： An electrical idle detection circuit including a full wave rectifier and a first amplifier. The full wave rectifier is configured to receive differential input signals and provide a rectified output signal based on the differential input signals. The first amplifier is configured to receive a first input signal based on the rectified output signal and a second input signal based on a reference signal. The first amplifier is configured to provide an output signal that indicates the differential input signals are one of active and in electrical idle based on the first input signal and the second input signal.
摘要翻译： 一种包括全波整流器和第一放大器的电怠速检测电路。 全波整流器配置为接收差分输入信号，并根据差分输入信号提供整流输出信号。 第一放大器被配置为基于经整流的输出信号接收第一输入信号，并且基于参考信号接收第二输入信号。 第一放大器被配置为提供输出信号，其基于第一输入信号和第二输入信号来指示差分输入信号是有效和电空闲之一。
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公开(公告)号：US20070252648A1
公开(公告)日：2007-11-01
申请号：US11411388
申请日：2006-04-26
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F2203/45028 , H03F2203/45548
摘要： An operational amplifier including a first current mirror, a second current mirror, and a differential pair of transistors. The differential pair of transistors are configured to receive two inputs to direct current through the first current mirror and the second current mirror. The first current mirror provides a first current to a first high impedance node and the second current mirror provides a second current to a second high impedance node.
摘要翻译： 一种运算放大器，包括第一电流镜，第二电流镜和差分对晶体管。 晶体管的差分对被配置为接收两个输入以将电流引导通过第一电流镜和第二电流镜。 第一电流镜向第一高阻抗节点提供第一电流，而第二电流镜向第二高阻抗节点提供第二电流。
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公开(公告)号：US20090180335A1
公开(公告)日：2009-07-16
申请号：US12014452
申请日：2008-01-15
摘要： One embodiment provides an integrated circuit including a first circuit and a second circuit. The first circuit is configured to obtain a sample of a first clock via a second clock and provide a selected clock from multiple clocks based on the sample. The second circuit is configured to provide a first pointer clock based on the first clock and a second pointer clock based on the selected clock. An edge of the second pointer clock relative to an edge of the first pointer clock is limited to an uncertainty range of within one-half a first pointer clock cycle.
摘要翻译： 一个实施例提供了包括第一电路和第二电路的集成电路。 第一电路被配置为经由第二时钟获得第一时钟的采样，并且基于该采样从多个时钟提供选定的时钟。 第二电路被配置为基于第一时钟提供第一指针时钟，并且基于所选择的时钟提供第二指针时钟。 相对于第一指针时钟的边缘的第二指针时钟的边缘被限制在第一指针时钟周期的二分之一内的不确定性范围。
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10.发明申请INTEGRATED CIRCUIT INCLUDING IMPEDANCE TO PROVIDE SYMMETRICAL DIFFERENTIAL SIGNALS 审中-公开集成电路，包括阻抗提供对称差分信号公开(公告)号：US20090160559A1
公开(公告)日：2009-06-25
申请号：US11960036
申请日：2007-12-19
申请人： Luca Ravezzi , Hamid Partovi
发明人： Luca Ravezzi , Hamid Partovi
IPC分类号： H03F3/04
CPC分类号： H03F3/45183 , H03F2203/45148 , H03F2203/45166 , H03H11/32
摘要： One embodiment provides an integrated circuit including an input stage and an impedance. The input stage is configured to receive a single-ended input signal and provide a differential output signal. The impedance is configured to receive the single-ended input signal and provide compensation to the input stage to provide symmetrical differential signals in the differential output signal.
摘要翻译： 一个实施例提供了包括输入级和阻抗的集成电路。 输入级被配置为接收单端输入信号并提供差分输出信号。 阻抗被配置为接收单端输入信号，并向输入级提供补偿，以在差分输出信号中提供对称的差分信号。
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