公开(公告)号：US20180097484A1

公开(公告)日：2018-04-05

申请号：US15809502

申请日：2017-11-10

申请人： Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.V.

发明人： Friedbert van Raay

IPC分类号： H03F3/21 ,  H03F1/56 ,  H03F3/60 ,  H03F3/195

CPC分类号： H03F3/211 ,  H01Q23/00 ,  H03F1/523 ,  H03F1/56 ,  H03F1/565 ,  H03F3/195 ,  H03F3/245 ,  H03F3/423 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/604 ,  H03F3/607 ,  H03F2200/06 ,  H03F2200/108 ,  H03F2200/135 ,  H03F2200/181 ,  H03F2200/222 ,  H03F2200/255 ,  H03F2200/297 ,  H03F2200/301 ,  H03F2200/315 ,  H03F2200/318 ,  H03F2200/387 ,  H03F2200/42 ,  H03F2200/423 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/498 ,  H03F2200/75 ,  H03F2203/45138 ,  H03F2203/45148 ,  H03F2203/45151 ,  H03F2203/45156 ,  H03F2203/45166 ,  H03F2203/45202 ,  H03F2203/45208 ,  H03F2203/45224 ,  H03F2203/45258 ,  H03F2203/45338 ,  H03F2203/45458 ,  H03F2203/45488 ,  H03F2203/45496 ,  H03F2203/45528 ,  H03F2203/45544 ,  H03F2203/45594 ,  H03F2203/45631 ,  H03F2203/45696 ,  H03F2203/45702

摘要： A power amplifier includes a two-dimensional matrix of N×M active cells formed by stacking main terminals of multiple active cells in series. The stacks are coupled in parallel to form the two-dimensional matrix. The power amplifier includes a driver structure to coordinate the driving of the active cells so that the effective output power of the two-dimensional matrix is approximately N×M the output power of each of the active cells.

公开(公告)号：US20170123443A1

公开(公告)日：2017-05-04

申请号：US15407284

申请日：2017-01-17

申请人： Dialog Semiconductor (UK) Limited

发明人： Frank Kronmueller ,  Ambreesh Bhattad

IPC分类号： G05F1/575 ,  H03F3/45 ,  H03F3/21

CPC分类号： G05F1/575 ,  H03F3/21 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/129 ,  H03F2203/45112 ,  H03F2203/45116 ,  H03F2203/45166 ,  H03F2203/45168 ,  H03F2203/45674

摘要： A voltage regulator is described. It comprises an amplification stage to control a voltage level of a first gain node and of a second gain node in response to an input voltage, to activate a first and a second output stage, respectively. It further comprises the first output stage to source a current at an output node of the voltage regulator from a first potential. The voltage regulator comprises the second output stage to sink a current at the output node to a second potential. The voltage regulator comprises a first operating point control circuit to set the voltage level of the first gain node such that a first maintenance current is sourced by the first output stage; and/or a second operating point control circuit to set the voltage level of the second gain node such that a second maintenance current is sunk by the second output stage.

公开(公告)号：US20160352295A1

公开(公告)日：2016-12-01

申请号：US15232056

申请日：2016-08-09

申请人： Maxlinear, Inc.

发明人： Abhishek Jajoo ,  Vamsi Paidi

IPC分类号： H03F3/45 ,  H03F3/195 ,  H03F1/52

CPC分类号： H03F3/45179 ,  H03F1/523 ,  H03F3/195 ,  H03F3/45188 ,  H03F2200/171 ,  H03F2200/222 ,  H03F2200/294 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/45166 ,  H03F2203/45386 ,  H03F2203/45464

摘要： Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA comprises differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may comprise: a first inductor with a first terminal capacitively-coupled to a gate terminal of a first transistor of the differential pair transistors and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first transistor of the differential pair transistors, the fourth inductor may be coupled to a source terminal of the second transistor of the differential pair transistors, and the third inductor may be capacitively-coupled to a gate terminal of the second transistor of the differential pair transistors and also to ground. The second inductor may be embedded within the first inductor.

摘要翻译： 用于Ku波段的伪差分低噪声放大器的方法和系统可以包括集成在半导体管芯上的低噪声放大器（LNA），其中LNA包括集成在半导体管芯上的嵌入式电感尾部的差分对晶体管。 嵌入式电感器尾部可以包括：第一电感器，其具有电容耦合到差分对晶体管的第一晶体管的栅极端子的第一端子和耦合到第二，第三和第四电感器的第一电感器的第二端子。 第二电感器可以耦合到差分对晶体管的第一晶体管的源极端子，第四电感器可以耦合到差分对晶体管的第二晶体管的源极端子，并且第三电感器可以电容耦合到 差分对晶体管的第二晶体管的栅极端子以及接地。 第二电感器可以嵌入在第一电感器内。

公开(公告)号：US08963640B2

公开(公告)日：2015-02-24

申请号：US13754267

申请日：2013-01-30

申请人： Samsung Electronics Co., Ltd.

发明人： Hyung-Tae Kim ,  Soo-Ik Cha

IPC分类号： H03F3/45 ,  H03F3/30

CPC分类号： H03F3/45179 ,  H03F3/3028 ,  H03F3/45219 ,  H03F2200/456 ,  H03F2203/45166

摘要： An amplifier for an output buffer includes an operational amplifier including a first input terminal, a second input terminal, and an output terminal, the operational amplifier is configured to generate an input bias current and amplify a voltage difference between signals applied to the first input terminal and the second input terminal, and to output the amplified voltage difference; and a self-bias circuit connected to the first input terminal and the second input terminal, the self-bias circuit is configured to generate first and second current paths when the voltage difference is equal to or greater than a predetermined voltage, to generate a tail current on the first or second current path, and to add the generated tail current to the input bias current of the operational amplifier, wherein the second input terminal is connected to the output terminal.

摘要翻译： 一种用于输出缓冲器的放大器，包括：运算放大器，包括第一输入端，第二输入端和输出端，运算放大器被配置为产生输入偏置电流，并放大施加到第一输入端的信号之间的电压差 和第二输入端，并输出放大的电压差; 以及与所述第一输入端子和所述第二输入端子连接的自偏置电路，所述自偏置电路被配置为当所述电压差等于或大于预定电压时产生第一和第二电流路径，以产生尾部 电流在第一或第二电流路径上，并且将产生的尾电流加到运算放大器的输入偏置电流，其中第二输入端连接到输出端。

公开(公告)号：US08890613B2

公开(公告)日：2014-11-18

申请号：US13718421

申请日：2012-12-18

申请人： SK Hynix Inc.

发明人： Tae-Jin Hwang

IPC分类号： H03F3/45

CPC分类号： H03F3/45076 ,  H03F3/45183 ,  H03F2203/45166 ,  H03F2203/45248 ,  H03F2203/45466 ,  H03F2203/45641 ,  H03F2203/45674

摘要： A signal amplification circuit includes a differential amplifier configured to receive a first signal and a second signal and generate an output signal, a differential amplifier configured to receive first and second signals and generate an output signal; and a controller configured to control an amount of current flowing in the differential amplifier using the output signal.

摘要翻译： 信号放大电路包括：差分放大器，被配置为接收第一信号和第二信号并产生输出信号;差分放大器，被配置为接收第一和第二信号并产生输出信号; 以及控制器，被配置为使用所述输出信号来控制在所述差分放大器中流动的电流量。

公开(公告)号：US20130266157A1

公开(公告)日：2013-10-10

申请号：US13857580

申请日：2013-04-05

申请人： MARVELL WORLD TRADE LTD.

发明人： Hao Zhou ,  Tao Shui ,  Yonghua Song ,  Yongxu Wang ,  Haiqing Zhang

IPC分类号： H03G3/20

CPC分类号： H03G3/20 ,  H03F1/083 ,  H03F1/34 ,  H03F3/21 ,  H03F3/45475 ,  H03F2200/03 ,  H03F2200/153 ,  H03F2200/408 ,  H03F2200/462 ,  H03F2203/45051 ,  H03F2203/45138 ,  H03F2203/45166 ,  H03F2203/45522 ,  H03F2203/45526 ,  H03G1/007 ,  H03G1/0088 ,  H03G3/3015 ,  H03G3/3026

摘要： Aspects of the disclosure process an amplifier circuit. The amplifier circuit includes an input stage, an intermediate stage, an output stage and a detecting and controlling circuit. The input stage is configured to receive an electrical signal for amplification. The intermediate stage is configured to amplify with an adjustable gain. The output stage is configured to drive an audio output device in response to the amplified electrical signal. The detecting and controlling circuit is configured to detect a current for driving the audio output device, and adjust the gain of the intermediate stage based on the current to compensate for a pole change of the amplifier circuit due to a change of the current.

摘要翻译： 披露过程的方面放大器电路。 放大器电路包括输入级，中间级，输出级和检测和控制电路。 输入级被配置为接收用于放大的电信号。 中间级被配置为以可调增益放大。 输出级被配置为响应于放大的电信号来驱动音频输出设备。 检测和控制电路被配置为检测用于驱动音频输出装置的电流，并且基于电流来调整中间级的增益，以补偿由于电流的变化引起的放大器电路的极点变化。

公开(公告)号：US20110133837A1

公开(公告)日：2011-06-09

申请号：US12899196

申请日：2010-10-06

申请人： Hiroshi KOMORI

发明人： Hiroshi KOMORI

IPC分类号： H03F3/45 ,  H03G3/30

CPC分类号： H03F3/45475 ,  H03F2203/45166 ,  H03F2203/45522 ,  H03F2203/45524 ,  H03F2203/45528 ,  H03G1/007

摘要： A gain variable range of a variable gain amplifier is increase and a non-linear distortion is reduced at the same time. The variable gain amplifier includes an operational amplifier, a variable resistive circuit which includes a plurality of variable resistive elements connected together in series, each having a resistance value corresponding to a given control voltage, and is connected between an input terminal and an output terminal of the operational amplifier, and a control circuit configured to generate a plurality of control voltages each corresponding to a gain control signal, having an offset corresponding to a DC voltage difference between input and output of the operational amplifier, and apply the plurality of control voltages to the plurality of the variable resistive elements, respectively.

摘要翻译： 可变增益放大器的增益可变范围增加，同时减少非线性失真。 可变增益放大器包括运算放大器，可变电阻电路，其包括串联连接在一起的多个可变电阻元件，每个可变电阻元件具有对应于给定控制电压的电阻值，并且连接在输入端子和输出端子之间 所述运算放大器和控制电路被配置为产生与增益控制信号对应的多个控制电压，所述增益控制信号具有对应于所述运算放大器的输入和输出之间的直流电压差的偏移量，并将所述多个控制电压施加到 多个可变电阻元件。

公开(公告)号：US07944292B1

公开(公告)日：2011-05-17

申请号：US12114491

申请日：2008-05-02

申请人： Ben Wee-Guan Tan

发明人： Ben Wee-Guan Tan

IPC分类号： H03F1/36

CPC分类号： H03F1/08 ,  H03F1/34 ,  H03F3/45475 ,  H03F2203/45116 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03F2203/45224 ,  H03F2203/45511 ,  H03F2203/45528 ,  H03F2203/45564 ,  H03F2203/45594 ,  H03F2203/45602

摘要： A feedback circuit disposed across input and output terminals of an amplifier is adapted so as not inject DC current back into the input terminal of the amplifier. The feedback circuit includes, in part, first and second current sources, a transistor, and a resistive load. The first current source supplies current to one of the terminals of the transistor in communication with an input terminal of the amplifier. The second current source receives this current and diverts it to a voltage supply. The transistor is maintained in the active region of operation. The resistive load has a first terminal in communication with an output terminal of the amplifier and a second terminal in communication with the transistor. The DC voltages at the two terminals of the resistive load are substantially equal so as to inhibit DC current flow therethrough.

摘要翻译： 设置在放大器的输入和输出端之间的反馈电路适于不将DC电流注入到放大器的输入端。 反馈电路部分地包括第一和第二电流源，晶体管和电阻负载。 第一电流源向与放大器的输入端通信的晶体管的一个端子提供电流。 第二电流源接收该电流并将其转移到电压源。 晶体管保持在有效的操作区域中。 电阻负载具有与放大器的输出端子通信的第一端子和与晶体管连通的第二端子。 电阻负载两端的直流电压基本上相等，从而阻止直流电流流经。

公开(公告)号：US07937601B2

公开(公告)日：2011-05-03

申请号：US12535814

申请日：2009-08-05

申请人： Greg Bakker ,  Khaled El-Ayat ,  Theodore Speers ,  Limin Zhu ,  Brian Schubert ,  Rabindranath Balasubramanian ,  Kurt Kilkind ,  Thomas Barraza ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

发明人： Greg Bakker ,  Khaled El-Ayat ,  Theodore Speers ,  Limin Zhu ,  Brian Schubert ,  Rabindranath Balasubramanian ,  Kurt Kilkind ,  Thomas Barraza ,  Venkatesh Narayanan ,  John McCollum ,  William C. Plants

IPC分类号： G06F1/30 ,  H03K19/173

CPC分类号： H03K19/1776 ,  G01K7/015 ,  G06F1/08 ,  G06F1/28 ,  G06F1/30 ,  G06F15/7842 ,  G06F15/7867 ,  H03F3/45475 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03K17/223 ,  H03K19/177 ,  H03K19/17732

摘要： A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

摘要翻译： 一种可编程片上系统集成电路装置，包括可编程逻辑块，非易失性存储块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块。 可编程互连架构包括可编程元件和互连导体。 可编程元件的一部分耦合到可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块，数字输入/输出电路块和互连导体，使得 可编程逻辑块，非易失性存储器块，模拟子系统，模拟输入/输出电路块和数字输入/输出电路块的输入和输出可以可编程地彼此耦合。

公开(公告)号：US20100327919A1

公开(公告)日：2010-12-30

申请号：US12823248

申请日：2010-06-25

申请人： Yutaka Oka

发明人： Yutaka Oka

IPC分类号： H03K3/00 ,  H03F3/45

CPC分类号： H03F3/45183 ,  H03F2203/45166 ,  H03F2203/45244 ,  H03F2203/45508 ,  H03F2203/45674

摘要： A differential amplifier main circuit amplifies, while first voltage is applied to drains of first and second transistors via a load circuit and second voltage is applied to source of third transistor, a difference between voltages applied to gates of the first and second transistors, and outputs it from a connection between the load circuit and drains of the first or second transistor. A voltage application circuit applies voltage to the gate of the third transistor so that a current between the source and drain thereof to have a predetermined magnitude. Gates of transistors of the application circuit are connected to a second common-connection of drains thereof to which the first voltage is applied via a load, the second voltage is applied to a first common-connection of sources of the transistors, and a connection of the second common-connection and the load is connected to the gate of the third transistor.

摘要翻译： 差分放大器主电路经由负载电路将第一电压施加到第一和第二晶体管的漏极并将第二电压施加到第三晶体管的源极时放大，施加到第一和第二晶体管的栅极的电压和输出之间的差 它来自负载电路和第一或第二晶体管的漏极之间的连接。 电压施加电路将电压施加到第三晶体管的栅极，使得其源极和漏极之间的电流具有预定的大小。 应用电路的晶体管的栅极连接到其第一共同连接的第一共同连接，第一共同连接的第一电压通过负载施加到第二共同连接，第二电压被施加到晶体管的源的第一共同连接， 第二共同连接和负载连接到第三晶体管的栅极。