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公开(公告)号：US20070025492A1
公开(公告)日：2007-02-01
申请号：US11171114
申请日：2005-06-30
IPC分类号： H04L23/00
CPC分类号： H04L25/0282
摘要： A source terminated serial link can recover from a low power mode by turning on multiple current-mode drivers in a phased sequence where the phased sequence is related to a resonant characteristic of a power supply net.
摘要翻译： 源端接串行链路可以通过在分相序列中打开多个电流模式驱动器从低功率模式恢复，其中相序序列与电源网络的谐振特性相关。
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公开(公告)号：US07245156B2
公开(公告)日：2007-07-17
申请号：US11094810
申请日：2005-03-31
IPC分类号： H03K19/0175
CPC分类号： H03K19/00323 , H03K19/018528
摘要： A pre-driver circuit includes a first stage to generate a first pre-driver signal and a second stage to generate a second pre-driver signal. The first and second stages are to generate the first and second pre-driver signals to cross at a point which reduces rise-and-fall mismatch in differential signal outputs from a current-mode driver.
摘要翻译： 预驱动器电路包括产生第一预驱动器信号的第一级和产生第二预驱动器信号的第二级。 第一和第二阶段是产生第一和第二预驱动器信号以在减少来自当前模式驱动器的差分信号输出的上升和下降失配的点处交叉。
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公开(公告)号：US20070071083A1
公开(公告)日：2007-03-29
申请号：US11237118
申请日：2005-09-28
IPC分类号： H03H7/30
CPC分类号： H04L25/0282 , H04L25/0276 , H04L25/0288
摘要： In one embodiment, the present invention includes a method for associating a first plurality of current sources with a first tap coefficient and associating a second plurality of current sources with a second tap coefficient. A first plurality of output switches coupled to the first plurality of current sources is gated using the first tap coefficient and a second plurality of output switches coupled to the second plurality of current sources is gated using the second tap coefficient. In such manner, the first and second plurality of equalized current sources may be driven onto an interconnect. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括用于将第一多个电流源与第一抽头系数相关联并将第二多个电流源与第二抽头系数相关联的方法。 耦合到第一多个电流源的第一多个输出开关使用第一抽头系数进行门控，并且使用第二抽头系数选择耦合到第二多个电流源的第二多个输出开关。 以这种方式，第一和第二多个均衡的电流源可以被驱动到互连上。 描述和要求保护其他实施例。
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公开(公告)号：US20060220674A1
公开(公告)日：2006-10-05
申请号：US11094810
申请日：2005-03-31
IPC分类号： H03K19/003
CPC分类号： H03K19/00323 , H03K19/018528
摘要： A pre-driver circuit includes a first stage to generate a first pre-driver signal and a second stage to generate a second pre-driver signal. The first and second stages are to generate the first and second pre-driver signals to cross at a point which reduces rise-and-fall mismatch in differential signal outputs from a current-mode driver.
摘要翻译： 预驱动器电路包括产生第一预驱动器信号的第一级和产生第二预驱动器信号的第二级。 第一和第二阶段是产生第一和第二预驱动器信号以在减少来自当前模式驱动器的差分信号输出的上升和下降失配的点处交叉。
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公开(公告)号：US06977537B2
公开(公告)日：2005-12-20
申请号：US10890332
申请日：2004-07-13
IPC分类号： H03D3/00 , H03L7/00 , H03L7/06 , H03L7/089 , H03L7/095 , H03L7/099 , H03L7/10 , H03L7/107 , H03L7/18
CPC分类号： H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/10 , H03L7/107 , H03L7/1072 , H03L7/18 , Y10S331/02
摘要： According to some embodiments, a low gain phase-locked loop circuit is provided.
摘要翻译： 根据一些实施例，提供了一种低增益锁相环电路。
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公开(公告)号：US06788155B2
公开(公告)日：2004-09-07
申请号：US10334276
申请日：2002-12-31
IPC分类号： H03L700
CPC分类号： H03L7/0898 , H03L7/095 , H03L7/099 , H03L7/10 , H03L7/107 , H03L7/1072 , H03L7/18 , Y10S331/02
摘要： A low gain phase-locked loop circuit comprising a phase detector, a plurality of voltage controlled oscillators, wherein each voltage controlled oscillator is selectable to provide an output clock signal based at least in part on information generated by the phase detector; and a multiplexer to output a signal generated by one of the voltage controlled oscillators as the output clock signal based on a multi-bit selection control signal.
摘要翻译： 一种低增益锁相环电路，包括相位检测器，多个压控振荡器，其中每个压控振荡器可选地至少部分地基于由相位检测器产生的信息来提供输出时钟信号; 以及多路复用器，其基于多位选择控制信号，输出由所述压控振荡器之一产生的信号作为所述输出时钟信号。
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