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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06498741B2

    公开(公告)日：2002-12-24

    申请号：US09746890

    申请日：2000-12-21

    申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

    发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

    IPC分类号： G11C506

    CPC分类号： G11C5/063

    摘要： A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

    摘要翻译： 提供一种半导体存储器件，其确保存储器数据传输时间和高速操作的对称性，并且具有大的写入/读取操作裕度，而不需要增加芯片面积。 通过在半导体芯片的垂直方向上的中间放置一个水平长的外围电路部分，将垂直长的移位寄存器部分设置在周边电路部分的上下方向并垂直于外围电路部分，并使存储器核心和移位寄存器装置在 水平方向，可以使存储器芯和移位寄存器部分之间的数据/信号线短，并且可以保持互连的对称性，这允许实现高速和大面积的半导体存储器件。 另外，通过将每个对应于数据块的移位寄存器堆叠并选择堆叠移位寄存器的顺序，使得外围电路与移位之间的互连长度可以获得更快的半导体存储器 寄存器被最小化。

    Semiconductor memory device
    2.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US06198649B1

    公开(公告)日：2001-03-06

    申请号：US09460641

    申请日：1999-12-15

    申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

    发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

    IPC分类号： G11C506

    CPC分类号： G11C5/063

    摘要： A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

    Semiconductor memory device inputting/outputting data synchronously with clock signal
    3.
    发明授权
    Semiconductor memory device inputting/outputting data synchronously with clock signal 有权
    半导体存储器件与时钟信号同步输入/输出数据

    公开(公告)号：US06801144B2

    公开(公告)日：2004-10-05

    申请号：US10678742

    申请日：2003-10-02

    申请人： Katsuki Matsudera ,  Masaru Koyanagi ,  Kazuhide Yoneya ,  Toshiki Hisada

    发明人： Katsuki Matsudera ,  Masaru Koyanagi ,  Kazuhide Yoneya ,  Toshiki Hisada

    IPC分类号： H03M900

    CPC分类号： G11C7/1036

    摘要： An input/output circuit inputs/outputs serial data. A register section comprises a first and a second register. The first register converts the serial data into parallel data. The second register converts parallel data into serial data. A first control signals supply a conversion timing for each bit when the serial data are converted into the parallel data. A second control signals supply a conversion timing for each bit when the parallel data are converted into the serial data. The signal generating circuit controls a timing of rise or fall of the first control signals and sets which of the memory cells should store a value for each bit, of the serial data, and controls a timing of rise or fall of the second control signals and sets which number of value of the serial data should be the value for each bit, of the parallel data read from the memory cells.

    摘要翻译： 输入/输出电路输入/输出串行数据。 寄存器部分包括第一和第二寄存器。 第一个寄存器将串行数据转换为并行数据。 第二个寄存器将并行数据转换为串行数据。 当串行数据被转换成并行数据时，第一控制信号为每个位提供转换定时。 当并行数据被转换成串行数据时，第二控制信号为每个位提供转换定时。 信号发生电路控制第一控制信号的上升或下降的定时，并设置哪个存储单元应存储串行数据的每个位的值，并且控制第二控制信号的上升或下降的定时，以及 将串行数据的值的数量设置为从存储器单元读取的并行数据的每个位的值。

    Semiconductor integrated circuit having output buffer
    5.
    发明授权
    Semiconductor integrated circuit having output buffer 失效

    公开(公告)号：US06563351B2

    公开(公告)日：2003-05-13

    申请号：US09965951

    申请日：2001-09-27

    申请人： Tadashi Onizawa ,  Natsuki Kushiyama ,  Masaru Koyanagi ,  Katsuki Matsudera

    发明人： Tadashi Onizawa ,  Natsuki Kushiyama ,  Masaru Koyanagi ,  Katsuki Matsudera

    IPC分类号： H03B100

    CPC分类号： H03K19/01707 ,  H03K17/102 ,  H03K17/162

    摘要： A semiconductor integrated circuit includes first and second MOS transistors and a capacitor. The first MOS transistor has a drain connected to an output terminal, a gate and a source. The second MOS transistor has a gate, a drain connected to the source of the first MOS transistor and a source and has the same conductivity type as the first MOS transistor. The capacitor has one electrode connected to the gate of the first MOS transistor and the other electrode connected to a node whose potential changes in a complementary fashion with respect to the drain potential of the first MOS transistor and functions to cancel out an influence, caused by the coupling of a mirror capacitor which exists between the gate and drain of the first MOS transistor, affecting the gate potential of the first MOS transistor.

    Semiconductor memory
    6.
    发明申请
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US20050152205A1

    公开(公告)日：2005-07-14

    申请号：US11013688

    申请日：2004-12-17

    申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Masaru Koyanagi

    发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Masaru Koyanagi

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C8/00

    CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1051 ,  G11C2207/107

    摘要： A semiconductor memory includes a converter configured to convert each read-data of plural bits read from a memory core into serial data, respectively, in synchronization with a read clock to generate converted read-data. An output register holds the converted read-data in synchronization with the read clock. A selector selects one bit from each plural bits of the converted read-data, in accordance with a control data, and to supply the selected bit to the output register.

    摘要翻译： 半导体存储器包括：转换器，被配置为与读取时钟同步地分别将从存储器芯读取的多个位的每个读取数据转换为串行数据，以产生转换的读取数据。 输出寄存器与读取时钟同步地保存转换的读取数据。 选择器根据控制数据从转换的读取数据的每个多个比特中选择一个比特，并将所选择的比特提供给输出寄存器。

    Semiconductor memory
    7.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US07206242B2

    公开(公告)日：2007-04-17

    申请号：US11013688

    申请日：2004-12-17

    申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Masaru Koyanagi

    发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Masaru Koyanagi

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1066 ,  G11C7/1006 ,  G11C7/1051 ,  G11C2207/107

    摘要： A semiconductor memory includes a converter configured to convert each read-data of plural bits read from a memory core into serial data, respectively, in synchronization with a read clock to generate converted read-data. An output register holds the converted read-data in synchronization with the read clock. A selector selects one bit from each plural bits of the converted read-data, in accordance with a control data, and to supply the selected bit to the output register.

    摘要翻译： 半导体存储器包括：转换器，被配置为与读取时钟同步地分别将从存储器芯读取的多个位的每个读取数据转换为串行数据，以产生转换的读取数据。 输出寄存器与读取时钟同步地保存转换的读取数据。 选择器根据控制数据从转换的读取数据的每个多个比特中选择一个比特，并将所选择的比特提供给输出寄存器。

    Dynamic random access memory device and semiconductor integrated circuit device
    8.
    发明授权
    Dynamic random access memory device and semiconductor integrated circuit device 有权
    动态随机存取存储器件和半导体集成电路器件

    公开(公告)号：US06496442B2

    公开(公告)日：2002-12-17

    申请号：US10076558

    申请日：2002-02-19

    申请人： Masaru Koyanagi ,  Kaoru Nakagawa ,  Takahiko Hara ,  Satoru Takase

    发明人： Masaru Koyanagi ,  Kaoru Nakagawa ,  Takahiko Hara ,  Satoru Takase

    IPC分类号： G11C800

    CPC分类号： G11C8/18 ,  G11C8/12 ,  G11C11/406

    摘要： A DRAM, including a plurality of banks each having a plurality of sub-arrays, and sense amplifier circuits commonly shared by sub-arrays in different banks, has a row access mode for activating a sub-array selected from each bank for reading or writing data, and a refresh mode for activating a plurality of sub-arrays in each bank and refreshing memory cell data therein at substantially the same timing. Sub-arrays in each bank activated at substantially the same timing in the refresh mode are more than sub-arrays in each bank activated in the row access model. Thereby, occurrence of operation constrains is minimized to ensure high-speed operation and improve the system performance of DRAMs employing the non-independent bank system.

    摘要翻译： 包括多个具有多个子阵列的多个存储体的DRAM和通常由不同存储体中的子阵列共享的读出放大器电路具有用于激活从每个存储体中选择的用于读取或写入的子阵列的行访问模式 数据和刷新模式，用于激活每个存储体中的多个子阵列，并以基本相同的定时刷新存储器单元数据。 在刷新模式中基本上相同的定时激活的每个存储体中的子阵列多于在行存取模型中激活的每个存储体中的子阵列。 由此，操作约束的发生被最小化以确保高速操作，并且提高采用非独立银行系统的DRAM的系统性能。