公开(公告)号：US06801144B2

公开(公告)日：2004-10-05

申请号：US10678742

申请日：2003-10-02

申请人： Katsuki Matsudera ,  Masaru Koyanagi ,  Kazuhide Yoneya ,  Toshiki Hisada

发明人： Katsuki Matsudera ,  Masaru Koyanagi ,  Kazuhide Yoneya ,  Toshiki Hisada

IPC分类号： H03M900

CPC分类号： G11C7/1036

摘要： An input/output circuit inputs/outputs serial data. A register section comprises a first and a second register. The first register converts the serial data into parallel data. The second register converts parallel data into serial data. A first control signals supply a conversion timing for each bit when the serial data are converted into the parallel data. A second control signals supply a conversion timing for each bit when the parallel data are converted into the serial data. The signal generating circuit controls a timing of rise or fall of the first control signals and sets which of the memory cells should store a value for each bit, of the serial data, and controls a timing of rise or fall of the second control signals and sets which number of value of the serial data should be the value for each bit, of the parallel data read from the memory cells.

摘要翻译： 输入/输出电路输入/输出串行数据。 寄存器部分包括第一和第二寄存器。 第一个寄存器将串行数据转换为并行数据。 第二个寄存器将并行数据转换为串行数据。 当串行数据被转换成并行数据时，第一控制信号为每个位提供转换定时。 当并行数据被转换成串行数据时，第二控制信号为每个位提供转换定时。 信号发生电路控制第一控制信号的上升或下降的定时，并设置哪个存储单元应存储串行数据的每个位的值，并且控制第二控制信号的上升或下降的定时，以及 将串行数据的值的数量设置为从存储器单元读取的并行数据的每个位的值。

公开(公告)号：US06498741B2

公开(公告)日：2002-12-24

申请号：US09746890

申请日：2000-12-21

申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

IPC分类号： G11C506

CPC分类号： G11C5/063

摘要： A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

摘要翻译： 提供一种半导体存储器件，其确保存储器数据传输时间和高速操作的对称性，并且具有大的写入/读取操作裕度，而不需要增加芯片面积。 通过在半导体芯片的垂直方向上的中间放置一个水平长的外围电路部分，将垂直长的移位寄存器部分设置在周边电路部分的上下方向并垂直于外围电路部分，并使存储器核心和移位寄存器装置在 水平方向，可以使存储器芯和移位寄存器部分之间的数据/信号线短，并且可以保持互连的对称性，这允许实现高速和大面积的半导体存储器件。 另外，通过将每个对应于数据块的移位寄存器堆叠并选择堆叠移位寄存器的顺序，使得外围电路与移位之间的互连长度可以获得更快的半导体存储器 寄存器被最小化。

公开(公告)号：US06198649B1

公开(公告)日：2001-03-06

申请号：US09460641

申请日：1999-12-15

申请人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

发明人： Katsuki Matsudera ,  Kazuhide Yoneya ,  Toshiki Hisada ,  Masaru Koyanagi ,  Natsuki Kushiyama ,  Kaoru Nakagawa ,  Takahiko Hara

IPC分类号： G11C506

CPC分类号： G11C5/063

摘要： A semiconductor memory device is provided which ensures the symmetry of memory data transmission time and a high-speed operation and has large write/read operation margin with no need of increasing the chip area. By placing a horizontally long peripheral circuit section in the middle in the vertical direction of a semiconductor chip, placing a vertically long shift register section above and below and perpendicularly to the peripheral circuit section, and making the memory core and shift register arrangement symmetrical in the horizontal direction, the data/signal lines between the memory core and the shift register section can be made short and the symmetry of the interconnections can be maintained, which allows the implementation of a high-speed and large-margin semiconductor memory device. In addition, a faster semiconductor memory can be obtained by forming the shift register section by stacking shift registers each corresponding to a data block and selecting the order in which the shift registers are stacked so that the length of interconnections between the peripheral circuit and the shift register is minimized.

公开(公告)号：US06510087B2

公开(公告)日：2003-01-21

申请号：US09963805

申请日：2001-09-25

申请人： Manami Kudou ,  Kazuhide Yoneya ,  Masaru Koyanagi ,  Toshiki Hisada ,  Katsuki Matsudera

发明人： Manami Kudou ,  Kazuhide Yoneya ,  Masaru Koyanagi ,  Toshiki Hisada ,  Katsuki Matsudera

IPC分类号： G11C700

CPC分类号： G11C7/106 ,  G11C7/1036 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/222 ,  G11C2207/108 ,  G11C2207/2281

摘要： A semiconductor memory device comprises a memory cell array, a first latch circuit group, and a second latch circuit group. The first latch circuit group sequentially outputs n/2 bit read data of n-bit read data from the memory cell array in response to sequentially shifted read control signals. The second latch circuit group sequentially outputs the remaining n/2 bit read data in response to the sequentially shifted read control signal.

公开(公告)号：US09129688B2

公开(公告)日：2015-09-08

申请号：US13608713

申请日：2012-09-10

申请人： Katsuaki Isobe ,  Noboru Shibata ,  Toshiki Hisada

发明人： Katsuaki Isobe ,  Noboru Shibata ,  Toshiki Hisada

IPC分类号： G11C16/16 ,  G11C16/04 ,  H01L27/115

CPC分类号： G11C16/16 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/1095

摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

摘要翻译： 根据一个实施例，形成在衬底中的第一导电类型的第一阱。 第二导电类型的第二阱形成在第一阱中。 多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是 布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

公开(公告)号：US08630106B2

公开(公告)日：2014-01-14

申请号：US12695623

申请日：2010-01-28

申请人： Takatoshi Minamoto ,  Toshiki Hisada ,  Dai Nakamura

发明人： Takatoshi Minamoto ,  Toshiki Hisada ,  Dai Nakamura

IPC分类号： G11C5/06

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M

摘要翻译： 半导体存储器件包括存储单元单元，字线，驱动电路和第一晶体管。 字线连接到第0至第N个存储单元的控制栅极。 第（N + 1）个第一晶体管的数量分别将电压转移到字线。 将电压转移到第i个（i是0到N的范围内的自然数）字线的第一晶体管中的一个以上，靠近第i个字线的字线的M（M

公开(公告)号：US08243491B2

公开(公告)日：2012-08-14

申请号：US12884378

申请日：2010-09-17

申请人： Toshiki Hisada ,  Hiromitsu Mashita

发明人： Toshiki Hisada ,  Hiromitsu Mashita

IPC分类号： G11C5/06

CPC分类号： G11C16/0483 ,  G11C7/18 ,  G11C2207/002 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529

摘要： According to one embodiment, a memory cell array includes memory cells arranged at crossing points of bit lines and word lines. The bit lines include first, second, third, and fourth bit lines sequentially arranged. A first sense circuit is arranged on a first end side of the memory cell array, electrically connected to the first and third bit lines. A second sense circuit is arranged on a second end side of the memory cell array, electrically connected to the second and fourth bit lines. A first hookup region is arranged between the memory cell array and the first sense circuit and includes a first transfer transistor connected to the first bit line and the first sense circuit. A second hookup region is arranged between the first hookup region and the first sense circuit and includes a second transfer transistor connected to the third bit line and the first sense circuit.

摘要翻译： 根据一个实施例，存储单元阵列包括布置在位线和字线的交叉点处的存储单元。 位线包括顺序排列的第一，第二，第三和第四位线。 第一感测电路布置在存储单元阵列的第一端侧，电连接到第一和第三位线。 第二感测电路布置在存储单元阵列的第二端侧上，电连接到第二和第四位线。 第一连接区域布置在存储单元阵列和第一感测电路之间，并且包括连接到第一位线和第一感测电路的第一传输晶体管。 第二连接区域布置在第一连接区域和第一感测电路之间，并且包括连接到第三位线和第一感测电路的第二传输晶体管。

公开(公告)号：US20120001331A1

公开(公告)日：2012-01-05

申请号：US13051652

申请日：2011-03-18

申请人： Takayuki Toba ,  Tohru Ozaki ,  Toshiki Hisada ,  Hiromitsu Mashita ,  Takafumi Taguchi

发明人： Takayuki Toba ,  Tohru Ozaki ,  Toshiki Hisada ,  Hiromitsu Mashita ,  Takafumi Taguchi

IPC分类号： H01L23/485 ,  H01L21/28

CPC分类号： H01L21/76816 ,  H01L27/0207 ,  H01L27/11519 ,  H01L27/11531 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a plurality of first interconnects, a second interconnect, a third interconnect, and a plurality of conductive members. The plurality of first interconnects are arranged periodically to extend in one direction. The second interconnect is disposed outside a group of the plurality of first interconnects to extend in the one direction. The third interconnect is provided between the group and the second interconnect. The plurality of conductive members are disposed on a side opposite to the group as viewed from the second interconnect. A shortest distance between the first interconnect and the third interconnect, a shortest distance between the third interconnect and the second interconnect, and a shortest distance between the first interconnects are equal. A shortest distance between the second interconnect and the conductive member is longer than the shortest distance between the first interconnects.

摘要翻译： 根据一个实施例，半导体器件包括多个第一互连，第二互连，第三互连和多个导电构件。 多个第一互连周期性地布置成在一个方向上延伸。 第二互连设置在多个第一互连的一组之外，以在一个方向上延伸。 第三互连设置在组和第二互连之间。 多个导电构件设置在从第二互连件观察的与组相反的一侧上。 第一互连和第三互连之间的最短距离，第三互连和第二互连之间的最短距离以及第一互连之间的最短距离相等。 第二互连和导电构件之间的最短距离比第一互连之间的最短距离长。

公开(公告)号：US20130003461A1

公开(公告)日：2013-01-03

申请号：US13608713

申请日：2012-09-10

申请人： Katsuaki ISOBE ,  Noboru Shibata ,  Toshiki Hisada

发明人： Katsuaki ISOBE ,  Noboru Shibata ,  Toshiki Hisada

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/16 ,  G11C5/025 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/1095

摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

摘要翻译： 根据一个实施例，形成在衬底中的第一导电类型的第一阱。 第二导电类型的第二阱形成在第一阱中。 多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是 布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

公开(公告)号：US08243524B2

公开(公告)日：2012-08-14

申请号：US12723864

申请日：2010-03-15

申请人： Yuya Suzuki ,  Toshiki Hisada ,  Yoshikazu Hosomura

发明人： Yuya Suzuki ,  Toshiki Hisada ,  Yoshikazu Hosomura

IPC分类号： G11C16/06

CPC分类号： G11C8/10 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526

摘要： A semiconductor storage device has a sense amplifier. The sense amplifier includes a first lower interconnection; a second interlayer insulation film formed on the first interlayer insulation film and top of the first interconnection; a contact interconnection formed in a direction perpendicular to a substrate plane of the semiconductor substrate so as to pass through the second interlayer insulation film, and connected to the first lower interconnection; a first upper interconnection formed on the second interlayer insulation film and connected to the contact interconnection disposed under the first upper interconnection; a dummy contact interconnection formed in a direction perpendicular to the substrate plane of the semiconductor substrate in the second interlayer insulation film, and adjacent to the contact interconnection; and a second upper interconnection formed on the second interlayer insulation film so as to extend in the first direction, and connected to the dummy contact interconnection disposed under the second upper interconnection.

摘要翻译： 半导体存储装置具有读出放大器。 读出放大器包括第一下部互连; 形成在第一层间绝缘膜上的第二层间绝缘膜和第一互连的顶部; 形成在与半导体衬底的衬底平面垂直的方向上以便穿过第二层间绝缘膜并且连接到第一下互连的接触互连; 形成在所述第二层间绝缘膜上并连接到设置在所述第一上部互连件下方的所述接触互连的第一上互连; 在第二层间绝缘膜中与垂直于半导体衬底的衬底平面的方向形成的虚拟接触互连，并且与接触互连相邻; 以及形成在所述第二层间绝缘膜上以沿所述第一方向延伸的第二上部互连件，并且连接到设置在所述第二上部互连件下方的所述虚拟接触互连件。