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公开(公告)号：US20050080762A1
公开(公告)日：2005-04-14
申请号：US10961299
申请日：2004-10-08
申请人： Katsuya Nakashima , Hideki Hara , Takashi Akai , Toshifumi Nomura , Kazumi Sato , Yukihisa Tsuneda , Toshiyuki Nishihara
发明人： Katsuya Nakashima , Hideki Hara , Takashi Akai , Toshifumi Nomura , Kazumi Sato , Yukihisa Tsuneda , Toshiyuki Nishihara
CPC分类号： G06F11/1435 , G11C13/0007 , G11C2213/31
摘要： A file storage apparatus capable of restoring integrity of file management information even when a power supply abnormality occurs without lowering the write speed. When updating meta data stored in an HDD, log data for reconstructing the meta data after update from the meta data before update is written into a non-volatile RAM (NVRAM), then, after this writing is completed, the update is executed. Accordingly, even when the update use meta data temporarily stored in a cache memory is partially lost due to trouble such as a power supply abnormality and when update of the meta data of a hard disk is incomplete, the log data corresponding to the meta data for the update is held in the NVRAM, so it becomes possible to restore the integrity of the meta data on the hard disk by using this log data.
摘要翻译： 即使在电源异常发生而不降低写入速度的情况下，也能够恢复文件管理信息的完整性的文件存储装置。 当更新存储在HDD中的元数据时，用于将更新后的元数据重新构建的更新前的元数据的日志数据写入非易失性RAM（NVRAM）中，则在写入完成之后，执行更新。 因此，即使当由于诸如电源异常的故障而暂时存储在高速缓冲存储器中的元数据部分地丢失，并且当硬盘的元数据的更新不完整时，即使对应于用于 该更新被保存在NVRAM中，因此可以通过使用该日志数据恢复硬盘上的元数据的完整性。
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2.发明授权公开(公告)号：US07640388B2
公开(公告)日：2009-12-29
申请号：US10961299
申请日：2004-10-08
申请人： Katsuya Nakashima , Hideki Hara , Takashi Akai , Toshifumi Nomura , Kazumi Sato , Yukihisa Tsuneda , Toshiyuki Nishihara
发明人： Katsuya Nakashima , Hideki Hara , Takashi Akai , Toshifumi Nomura , Kazumi Sato , Yukihisa Tsuneda , Toshiyuki Nishihara
IPC分类号： G06F13/10
CPC分类号： G06F11/1435 , G11C13/0007 , G11C2213/31
摘要： A file storage apparatus capable of restoring integrity of file management information even when a power supply abnormality occurs without lowering the write speed. When updating meta data stored in an HDD, log data for reconstructing the meta data after update from the meta data before update is written into a non-volatile RAM (NVRAM), then, after this writing is completed, the update is executed. Accordingly, even when the update use meta data temporarily stored in a cache memory is partially lost due to trouble such as a power supply abnormality and when update of the meta data of a hard disk is incomplete, the log data corresponding to the meta data for the update is held in the NVRAM, so it becomes possible to restore the integrity of the meta data on the hard disk by using this log data.
摘要翻译： 即使在电源异常发生而不降低写入速度的情况下，也能够恢复文件管理信息的完整性的文件存储装置。 当更新存储在HDD中的元数据时，用于将更新后的元数据重新构建的更新前的元数据的日志数据写入非易失性RAM（NVRAM）中，则在写入完成之后，执行更新。 因此，即使当由于诸如电源异常的故障而暂时存储在高速缓冲存储器中的元数据部分地丢失，并且当硬盘的元数据的更新不完整时，即使对应于用于 该更新被保存在NVRAM中，因此可以通过使用该日志数据恢复硬盘上的元数据的完整性。
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3.发明授权Ferroelectric memory capable of continuously fast transferring data words in a pipeline 失效铁电存储器能够连续快速地传输流水线中的数据字公开(公告)号：US07310262B2
公开(公告)日：2007-12-18
申请号：US11507509
申请日：2006-08-22
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling data access, wherein the control part accesses data by a first processing of reading out a plurality of words of data from memory cells of a word line and a plate line selected according to a row address and storing it in the sense amplifiers, a second processing of selecting sense amplifiers from the column address and inputting/outputting data with the outside, and a third processing of writing back the data of the sense amplifiers into the memory cells, with data being continuously input or output and transferred by repeatedly executing the second processing using the column address generated in the internal counter for a group of words read out to the sense amplifiers at the first processing, and a file storage device and a computer system utilizing such a ferroelectric memory.
摘要翻译： 一种存储装置，包括：包括多个存储单元的铁电存储单元阵列; 连接到位线并由列地址选择的读出放大器; 一个能产生列地址的内部计数器; 以及控制数据访问的控制部分，其中控制部分通过从根据行地址选择的字线和板线的存储器单元中读出多个数据字的第一处理访问数据并将其存储在该意义上 放大器，从列地址中选择读出放大器并与外部输入/输出数据的第二处理，以及将读出放大器的数据写入存储单元的第三处理，数据被连续地输入或输出并由 使用在内部计数器中产生的列地址重复执行第二处理，用于在第一处理期间读出到读出放大器的一组字，以及文件存储装置和利用这种铁电存储器的计算机系统。
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公开(公告)号：US07565588B2
公开(公告)日：2009-07-21
申请号：US11607029
申请日：2006-12-01
申请人： Katsuya Nakashima , Kazuhiro Suzuki , Satoshi Yamakawa , Toshiyuki Nishihara , Yukihisa Tsuneda
发明人： Katsuya Nakashima , Kazuhiro Suzuki , Satoshi Yamakawa , Toshiyuki Nishihara , Yukihisa Tsuneda
CPC分类号： G11C7/1036 , G11C7/1039 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/846 , G11C2216/14
摘要： A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer configured to latch read data of the cell array in units of pages; an output circuit configured to output read data; and a data transfer circuit configured to sequentially transfer read data in units of pages latched in the buffer to the output circuit, wherein the data transfer circuit includes: at least one layer of a scan register train including a plurality of serially connected scan registers having a register and a multiplexer connected to each other to operate for each of clocks, wherein an output of the multiplexer is connected to an input of a register, and an input of a multiplexer is connected to an output of a register in a next previous stage.
摘要翻译： 提供半导体器件和数据存储装置。 半导体器件包括：单元阵列，配置成具有排列成阵列的数据存储单元; 至少一个缓冲器被配置为以页为单位来锁存所述单元阵列的读取数据; 输出电路，被配置为输出读取数据; 以及数据传送电路，被配置为将读取的数据以缓存器中的锁存的页面顺序地传送到输出电路，其中数据传送电路包括：至少一层扫描寄存器串，其包括多个串行连接的扫描寄存器， 寄存器和多路复用器相互连接以对每个时钟进行操作，其中多路复用器的输出连接到寄存器的输入，并且多路复用器的输入连接到下一个前一级的寄存器的输出。
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公开(公告)号：US20070130488A1
公开(公告)日：2007-06-07
申请号：US11607029
申请日：2006-12-01
申请人： Katsuya Nakashima , Kazuhiro Suzuki , Satoshi Yamakawa , Toshiyuki Nishihara , Yukihisa Tsuneda
发明人： Katsuya Nakashima , Kazuhiro Suzuki , Satoshi Yamakawa , Toshiyuki Nishihara , Yukihisa Tsuneda
CPC分类号： G11C7/1036 , G11C7/1039 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/846 , G11C2216/14
摘要： A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer configured to latch read data of the cell array in units of pages; an output circuit configured to output read data; and a data transfer circuit configured to sequentially transfer read data in units of pages latched in the buffer to the output circuit, wherein the data transfer circuit includes: at least one layer of a scan register train including a plurality of serially connected scan registers having a register and a multiplexer connected to each other to operate for each of clocks, wherein an output of the multiplexer is connected to an input of a register, and an input of a multiplexer is connected to an output of a register in a next previous stage.
摘要翻译： 提供半导体器件和数据存储装置。 半导体器件包括：单元阵列，配置成具有排列成阵列的数据存储单元; 至少一个缓冲器被配置为以页为单位来锁存所述单元阵列的读取数据; 输出电路，被配置为输出读取数据; 以及数据传送电路，被配置为将读取的数据以缓存器中的锁存的页面顺序地传送到输出电路，其中数据传送电路包括：至少一层扫描寄存器串，其包括多个串行连接的扫描寄存器， 寄存器和多路复用器相互连接以对每个时钟进行操作，其中多路复用器的输出连接到寄存器的输入，并且多路复用器的输入连接到下一个前一级的寄存器的输出。
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公开(公告)号：US20070041234A1
公开(公告)日：2007-02-22
申请号：US11507509
申请日：2006-08-22
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling data access, wherein the control part accesses data by a first processing of reading out a plurality of words of data from memory cells of a word line and a plate line selected according to a row address and storing it in the sense amplifiers, a second processing of selecting sense amplifiers from the column address and inputting/outputting data with the outside, and a third processing of writing back the data of the sense amplifiers into the memory cells, data being continuously input or output and transferred by repeatedly executing the second processsing using the column address generated in the internal counter for a group of words read out to the sense amplifiers at the first processing,and a file storage device and a computer system utilizing such a ferroelectric memory.
摘要翻译： 一种存储装置，包括：包括多个存储单元的铁电存储单元阵列; 连接到位线并由列地址选择的读出放大器; 一个能产生列地址的内部计数器; 以及控制数据访问的控制部分，其中控制部分通过从根据行地址选择的字线和板线的存储器单元中读出多个数据字的第一处理访问数据并将其存储在该意义上 放大器，从列地址中选择读出放大器并与外部输入/输出数据的第二处理，以及将读出放大器的数据写回存储单元的第三处理，数据被连续地输入或输出并重复传送 使用在内部计数器中生成的列地址对在第一处理期间读出到读出放大器的一组单词执行第二处理，以及文件存储装置和利用这种铁电存储器的计算机系统。
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7.发明授权公开(公告)号：US07203086B2
公开(公告)日：2007-04-10
申请号：US11386843
申请日：2006-03-23
CPC分类号： G11C11/22
摘要： In a data reading method, a first reading pulse is applied to a memory cell to generate a first signal corresponding to data stored in the memory cell, reference signal generating data corresponding to a high level side is written to the memory cell, a second reading pulse is applied to the memory cell to generate a second signal corresponding to the reference signal generating data, and a reference signal is generated on the basis of the second signal. Then the first signal and the reference signal are compared with each other to determine the stored data stored in the memory cell. In data writing, high-level data is written to the memory cell without using a bit line.
摘要翻译： 在数据读取方法中，第一读取脉冲被施加到存储单元以产生对应于存储在存储单元中的数据的第一信号，对应于高电平侧的参考信号产生数据被写入存储单元，第二读数 脉冲被施加到存储器单元以产生对应于参考信号产生数据的第二信号，并且基于第二信号产生参考信号。 然后将第一信号和参考信号彼此进行比较，以确定存储在存储单元中的存储数据。 在数据写入中，高电平数据被写入存储单元，而不使用位线。
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8.发明申请公开(公告)号：US20060164878A1
公开(公告)日：2006-07-27
申请号：US11386843
申请日：2006-03-23
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： In a data reading method according to the present invention, a first reading pulse is applied to a memory cell to generate a first signal corresponding to data stored in the memory cell. Next, reference signal generating data corresponding to a high level side is written to the memory cell. Next, a second reading pulse is applied to the memory cell to generate a second signal corresponding to the reference signal generating data. Next, a reference signal is generated on the basis of the second signal. Then the first signal and the reference signal are compared with each other to determine the stored data stored in the memory cell. In data writing, high-level data is first written to the memory cell without using a bit line. A high-level or low-level signal corresponding to data to be written is applied to the bit line in advance. When a low-level signal is applied to the bit line, low-level data is written from the bit line to the memory cell. Thereby a reading operation margin is dramatically extended to prevent erroneous reading. Also, reading/writing operation can be performed at high speed and with low power consumption.
摘要翻译： 在根据本发明的数据读取方法中，第一读取脉冲被施加到存储器单元以产生对应于存储在存储单元中的数据的第一信号。 接下来，将对应于高电平侧的参考信号产生数据写入存储单元。 接下来，向存储单元施加第二读取脉冲，以产生对应于参考信号产生数据的第二信号。 接下来，基于第二信号生成参考信号。 然后将第一信号和参考信号彼此进行比较，以确定存储在存储单元中的存储数据。 在数据写入时，首先将高电平数据写入存储单元，而不使用位线。 预先将与要写入的数据对应的高电平或低电平信号施加到位线。 当低电平信号施加到位线时，低电平数据从位线写入存储单元。 因此，读取操作余量大大延长以防止错误读取。 此外，读/写操作可以以高速和低功耗进行。
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公开(公告)号：US06754095B2
公开(公告)日：2004-06-22
申请号：US10283313
申请日：2002-10-29
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A D/A converter capable of temporally controlling output of analog data during D/A conversion is provided. The digital to analog converter includes a ferroelectric non-volatile semiconductor memory. The ferroelectric non-volatile semiconductor memory includes a data line, a memory unit which has M memory cells, and M plate lines. Each of the memory cells includes a first electrode, a ferroelectric layer and a second electrode. The first electrode of the memory cells is shared in the memory unit and is connected to the data line. The second electrode of the mth memory cell is connected to the mth plate line. And the area of the ferroelectric layer of the memory cells varies among the memory cells.
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10.发明授权公开(公告)号：US07142444B2
公开(公告)日：2006-11-28
申请号：US10798413
申请日：2004-03-12
IPC分类号： G11C11/22 , G11C7/14 , G11C7/06 , G11C11/4193 , G11C11/4197 , G11C7/22
CPC分类号： G11C11/22
摘要： In a data reading method, a first reading pulse is applied to a memory cell to generate a first signal corresponding to data stored in the memory cell, reference signal generating data corresponding to a high level side is written to the memory cell, a second reading pulse is applied to the memory cell to generate a second signal corresponding to the reference signal generating data, and a reference signal is generated on the basis of the second signal. Then the first signal and the reference signal are compared with each other to determine the stored data stored in the memory cell. In data writing, high-level data is first written to the memory cell without using a bit line.
摘要翻译： 在数据读取方法中，第一读取脉冲被施加到存储单元以产生对应于存储在存储单元中的数据的第一信号，对应于高电平侧的参考信号产生数据被写入存储单元，第二读数 脉冲被施加到存储器单元以产生对应于参考信号产生数据的第二信号，并且基于第二信号产生参考信号。 然后将第一信号和参考信号彼此进行比较，以确定存储在存储单元中的存储数据。 在数据写入时，首先将高电平数据写入存储单元，而不使用位线。
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