公开(公告)号：US07052621B2

公开(公告)日：2006-05-30

申请号：US10461090

申请日：2003-06-13

申请人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

发明人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

IPC分类号： C23F1/00

CPC分类号： H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

公开(公告)号：US07241681B2

公开(公告)日：2007-07-10

申请号：US11330834

申请日：2006-01-12

申请人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

发明人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas C. La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew H. Simon ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

公开(公告)号：US07091612B2

公开(公告)日：2006-08-15

申请号：US10684952

申请日：2003-10-14

申请人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas C. La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

发明人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas C. La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

IPC分类号： H01L23/12 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

公开(公告)号：US07494915B2

公开(公告)日：2009-02-24

申请号：US11463447

申请日：2006-08-09

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

摘要翻译： 在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及 沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

公开(公告)号：US07122462B2

公开(公告)日：2006-10-17

申请号：US10707122

申请日：2003-11-21

申请人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

发明人： Lawrence A. Clevenger ,  Andrew P. Cowley ,  Timothy J. Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Erdem Kaltalioglu ,  Kaushik A. Kumar ,  Douglas C. La Tulipe, Jr. ,  Jochen Schacht ,  Andrew H. Simon ,  Terry A. Spooner ,  Yun-Yu Wang ,  Clement H. Wann ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

公开(公告)号：US20060113278A1

公开(公告)日：2006-06-01

申请号：US11330834

申请日：2006-01-12

申请人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew Simon ,  Mark Hoinkis ,  Steffen Kaldor ,  Chih-Chao Yang

发明人： Kaushik Kumar ,  Lawrence Clevenger ,  Timothy Dalton ,  Douglas La Tulipe ,  Andy Cowley ,  Erdem Kaltalioglu ,  Jochen Schacht ,  Andrew Simon ,  Mark Hoinkis ,  Steffen Kaldor ,  Chih-Chao Yang

IPC分类号： B44C1/22 ,  H01B13/00

CPC分类号： H01L21/76832 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L2221/1036 ,  Y10T428/12576 ,  Y10T428/12806 ,  Y10T428/265 ,  Y10T428/31678

摘要： A metal hardmask for use with a Dual Damascene process used in the manufacturing of semiconductor devices. The metal hardmask has advantageous translucent characteristics to facilitate alignment between levels while fabricating a semiconductor device and avoids the formation of metal oxide residue deposits. The metal hardmask comprises a first or primary layer of TiN (titanium nitride) and a second or capping layer of TaN (tantalum nitride).

摘要翻译： 用于制造半导体器件的双镶嵌工艺的金属硬掩模。 金属硬掩模具有有利的半透明特性，以有助于在制造半导体器件时水平之间的对准，并避免形成金属氧化物残留物沉积物。 金属硬掩模包括TiN（氮化钛）的第一或第一层和TaN（氮化钽）的第二或覆盖层。

公开(公告)号：US20050077628A1

公开(公告)日：2005-04-14

申请号：US10684952

申请日：2003-10-14

申请人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

发明人： Kaushik Kumar ,  Timothy Dalton ,  Larry Clevenger ,  Andy Cowley ,  Douglas La Tulipe ,  Mark Hoinkis ,  Chih-Chao Yang ,  Yi-Hsiung Lin ,  Erdem Kaltalioglu ,  Markus Naujok ,  Jochen Schacht

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76835 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A dual damascene structure and method of fabrication thereof. An insulating layer comprises a first dielectric material and a second dielectric material, the second dielectric material being different from the first dielectric material. First conductive regions having a first pattern are formed in the first dielectric material, and second conductive regions having a second pattern are formed in the second dielectric material, the second pattern being different from the first pattern. One of the first dielectric material and the second dielectric material comprises an organic material, and the other dielectric material comprises an inorganic material. One of the first and second dielectric materials is etchable selective to the other dielectric material. A method of cleaning a semiconductor wafer processing chamber while a wafer remains residing within the chamber is also disclosed.

公开(公告)号：US20060292852A1

公开(公告)日：2006-12-28

申请号：US11463447

申请日：2006-08-09

申请人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

摘要翻译： 在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及 沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

公开(公告)号：US20050112864A1

公开(公告)日：2005-05-26

申请号：US10707122

申请日：2003-11-21

申请人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe, Jr. ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe, Jr. ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

摘要翻译： 在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及 沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

公开(公告)号：US07241696B2

公开(公告)日：2007-07-10

申请号：US10318606

申请日：2002-12-11

申请人： Larry Clevenger ,  Timothy Joseph Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik Kumar ,  Douglas C. La Tulipe, Jr. ,  Soon-Cheon Seo ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Chih-Chao Yang ,  Haining Yang

发明人： Larry Clevenger ,  Timothy Joseph Dalton ,  Mark Hoinkis ,  Steffen K. Kaldor ,  Kaushik Kumar ,  Douglas C. La Tulipe, Jr. ,  Soon-Cheon Seo ,  Andrew Herbert Simon ,  Yun-Yu Wang ,  Chih-Chao Yang ,  Haining Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

摘要： Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor is covered by a capping layer and a dielectric layer. The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor. In the process of sputter etching, the capping layer is redeposited onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

摘要翻译： 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体被覆盖层和电介质层覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体。 在溅射蚀刻的过程中，覆盖层被再沉积到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。