公开(公告)号：US20070037403A1

公开(公告)日：2007-02-15

申请号：US11161599

申请日：2005-08-09

申请人： Kaushik Chanda ,  Lawrence Clevenger ,  Andrew Cowley ,  Jason Gill ,  Baozhen Li ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Lawrence Clevenger ,  Andrew Cowley ,  Jason Gill ,  Baozhen Li ,  Chih-Chao Yang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76865 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76886

摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.

摘要翻译： 制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。 该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。 该方法产生防止开路的结构。

公开(公告)号：US20070115018A1

公开(公告)日：2007-05-24

申请号：US11163948

申请日：2005-11-04

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US20060234497A1

公开(公告)日：2006-10-19

申请号：US11107074

申请日：2005-04-15

申请人： Chih-Chao Yang ,  Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Meeyoung Yoon

发明人： Chih-Chao Yang ,  Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Meeyoung Yoon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

公开(公告)号：US20050112862A1

公开(公告)日：2005-05-26

申请号：US10707119

申请日：2003-11-21

申请人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Kaushik Kumar ,  Stephen Rossnagel ,  Andrew Simon ,  Douglas La Tulipe

发明人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Kaushik Kumar ,  Stephen Rossnagel ,  Andrew Simon ,  Douglas La Tulipe

IPC分类号： G03F9/00 ,  H01L21/033 ,  H01L21/285 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/544

CPC分类号： H01L23/544 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2855 ,  H01L21/76841 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A hardmask layer in the back end of an integrated circuit is formed from TaN having a composition of less than 50% Ta and a resistivity greater than 400 μOhm-cm, so that it is substantially transparent in the visible and permits visual alignment of upper and lower alignment marks through the hardmask and intervening layer(s) of ILD. A preferred method of formation of the hardmask is by sputter deposition of Ta in an ambient containing N2 and a flow rate such that (N2 flow)/(N2+carrier flow)>0.5.

摘要翻译： 集成电路后端的硬掩模层由具有小于50％Ta且电阻率大于400μΩ·cm的组成的TaN形成，使得其在可见光中基本上是透明的并且允许上和 通过硬掩模和ILD的中间层降低对准标记。 形成硬掩模的优选方法是通过在含有N 2 O 2的环境中溅射沉积Ta并使流速使得（N 2 N 2 O 2）/（N _{2 +载体流）> 0.5。}

公开(公告)号：US20080107149A1

公开(公告)日：2008-05-08

申请号：US12004011

申请日：2007-12-19

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

IPC分类号： G01N25/72 ,  G01R31/26

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US20080014744A1

公开(公告)日：2008-01-17

申请号：US11860602

申请日：2007-09-25

申请人： Chih-Chao Yang ,  Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Meeyoung Yoon

发明人： Chih-Chao Yang ,  Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Meeyoung Yoon

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

公开(公告)号：US20080006944A1

公开(公告)日：2008-01-10

申请号：US11860590

申请日：2007-09-25

申请人： Chih-Chao Yang ,  Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Meeyoung Yoon

发明人： Chih-Chao Yang ,  Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Meeyoung Yoon

IPC分类号： H01L23/52

CPC分类号： H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

摘要翻译： 一种镶嵌线及其形成方法。 该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。 该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。

公开(公告)号：US20070059922A1

公开(公告)日：2007-03-15

申请号：US11162511

申请日：2005-09-13

申请人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Kaushik Kumar ,  Douglas La Tulipe ,  David Rath ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Kaushik Kumar ,  Douglas La Tulipe ,  David Rath ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76811 ,  H01L21/02063 ,  H01L21/76814 ,  H01L21/76835

摘要： The present invention relates to methods for post-etch, particularly post-RIE, removal of fluorocarbon-based residues from a hybrid dielectric structure. The hybrid dielectric structure contains a first dielectric material, and a line-level dielectric layer containing a second, different dielectric material, and wherein said second, different dielectric material comprises a polymeric thermoset dielectric material having a dielectric constant less than 4. Low energy electron beam or low temperature annealing is utilized by the present invention for removal of the fluorocarbon-based residues from such a hybrid dielectric structure, without damaging the low-k polymeric thermoset dielectric material contained in such a hybrid dielectric structure.

摘要翻译： 本发明涉及用于从混合电介质结构去除基于碳氟化合物的残留物的后蚀刻，特别是后RIE的方法。 混合电介质结构包含第一电介质材料和含有第二不同介电材料的线路级介电层，并且其中所述第二不同介电材料包含介电常数小于4的聚合物热固性介电材料。低能电子 本发明使用光束或低温退火来从这种混合电介质结构中除去基于碳氟化合物的残留物，而不会损坏这种混合电介质结构中所含的低k聚合物热固性介电材料。

公开(公告)号：US20050112864A1

公开(公告)日：2005-05-26

申请号：US10707122

申请日：2003-11-21

申请人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe, Jr. ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Andrew Cowley ,  Timothy Dalton ,  Mark Hoinkis ,  Steffen Kaldor ,  Erdem Kaltalioglu ,  Kaushik Kumar ,  Douglas La Tulipe, Jr. ,  Jochen Schacht ,  Andrew Simon ,  Terry Spooner ,  Yun-Yu Wang ,  Clement Wann ,  Chih-Chao Yang

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

摘要翻译： 在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及 沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

公开(公告)号：US20060281338A1

公开(公告)日：2006-12-14

申请号：US11160213

申请日：2005-06-14

申请人： Kaushik Chanda ,  Hazara Rathore ,  Paul McLaughlin ,  Robert Edwards ,  Lawrence Clevenger ,  Andrew Cowley ,  Chih-Chao Yang ,  Conrad Barile

发明人： Kaushik Chanda ,  Hazara Rathore ,  Paul McLaughlin ,  Robert Edwards ,  Lawrence Clevenger ,  Andrew Cowley ,  Chih-Chao Yang ,  Conrad Barile

IPC分类号： H01L21/00

CPC分类号： H01L22/14 ,  G01R31/2642 ,  G01R31/2831

摘要： The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.

摘要翻译： 本发明预测半导体中的过早的介质击穿。 对于半导体晶片计算至少一个绝缘击穿模式。 如果计算一种模式，则过早的介电击穿将与在所述计算模式中具有小于多个击穿电压的预定标准偏差的击穿电压的任何半导体相关联。 如果计算多个模式，则确定最准确地代表半导体晶片的电介质击穿的模式，并且过早的电介质击穿将与任何具有小于计算模式的预定标准的击穿电压的半导体相关联，其最准确地表示用于 半导体晶片。