公开(公告)号：US20100190317A1

公开(公告)日：2010-07-29

申请号：US12691483

申请日：2010-01-21

申请人： Kazuaki IWASAWA ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

发明人： Kazuaki IWASAWA ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

摘要翻译： 半导体器件制造方法在半导体衬底中具有形成元件隔离沟槽，在元件隔离沟槽的内部形成硅化合物膜，以便嵌入元件隔离沟槽，在第一温度下进行第一氧化处理以使表面 所述硅化合物膜能够通过氧化剂和杂质而不允许含有硅原子的挥发性物质通过的挥发性物质排放防止层，并且在比所述第一温度高的第二温度下进行第二氧化处理 温度以在元件隔离槽内形成被覆氧化硅膜。

公开(公告)号：US20120034754A1

公开(公告)日：2012-02-09

申请号：US13272457

申请日：2011-10-13

申请人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

发明人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

摘要翻译： 半导体器件制造方法在半导体衬底中具有形成元件隔离沟槽，在元件隔离沟槽的内部形成硅化合物膜，以便嵌入元件隔离沟槽，在第一温度下进行第一氧化处理以使表面 所述硅化合物膜能够通过氧化剂和杂质而不允许含有硅原子的挥发性物质通过的挥发性物质排放防止层，并且在比所述第一温度高的第二温度下进行第二氧化处理 温度以在元件隔离槽内形成被覆氧化硅膜。

公开(公告)号：US08080463B2

公开(公告)日：2011-12-20

申请号：US12691483

申请日：2010-01-21

申请人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

发明人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

摘要翻译： 半导体器件制造方法在半导体衬底中具有形成元件隔离沟槽，在元件隔离沟槽的内部形成硅化合物膜，以便嵌入元件隔离沟槽，在第一温度下进行第一氧化处理以使表面 所述硅化合物膜能够通过氧化剂和杂质而不允许含有硅原子的挥发性物质通过的挥发性物质排放防止层，并且在比所述第一温度高的第二温度下进行第二氧化处理 温度以在元件隔离槽内形成被覆氧化硅膜。

公开(公告)号：US08441061B2

公开(公告)日：2013-05-14

申请号：US12868450

申请日：2010-08-25

申请人： Takashi Nakao ,  Kazuaki Iwasawa

发明人： Takashi Nakao ,  Kazuaki Iwasawa

IPC分类号： H01L27/115

CPC分类号： H01L29/66477 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked structural body, a semiconductor pillar, and a memory unit. The stacked structural body is provided on a major surface of the substrate. The stacked structural body includes electrode films alternately stacked with inter-electrode insulating films in a direction perpendicular to the major surface. The pillar pierces the body in the direction. The memory unit is provided at an intersection between the pillar and the electrode films. The electrode films include at least one of amorphous silicon and polysilicon. The stacked structural body includes first and second regions. A distance from the second region to the substrate is greater than a distance from the first region to the substrate. A concentration of an additive included in the electrode film in the first region is different from that included in the electrode film in the second region.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括衬底，层叠结构体，半导体柱和存储单元。 层叠结构体设置在基板的主表面上。 叠层结构体包括在垂直于主表面的方向上交替层叠有电极间绝缘膜的电极膜。 支柱沿着方向刺穿身体。 存储单元设置在柱和电极膜之间的交点处。 电极膜包括非晶硅和多晶硅中的至少一种。 层叠结构体包括第一和第二区域。 从第二区域到基板的距离大于从第一区域到基板的距离。 包含在第一区域中的电极膜中的添加剂的浓度与第二区域中的电极膜中包含的添加剂的浓度不同。

公开(公告)号：US07863166B2

公开(公告)日：2011-01-04

申请号：US12646563

申请日：2009-12-23

申请人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

发明人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

IPC分类号： H01L21/20

CPC分类号： H01L27/115 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203 ,  H01L29/66825

摘要： A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

摘要翻译： 一种制造半导体存储装置的方法包括在形成在硅衬底上的绝缘膜中的多个位置提供开口部分，然后在其中形成开口部分的绝缘膜上形成非晶硅膜，并且在 开口部。 然后，形成沟槽，将相邻的开口部之间的中点附近的非晶硅膜分割成一个开口部侧的一部分和另一个开口部侧的一部分。 接着，对其中形成沟槽的非晶硅膜进行退火并进行固相结晶以形成具有用作晶种的开口部分的单晶，从而形成硅单晶层。 然后，在硅单晶层上形成存储单元阵列。

公开(公告)号：US20090273021A1

公开(公告)日：2009-11-05

申请号：US12432453

申请日：2009-04-29

申请人： Katsuyuki SEKINE ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Yoshio Ozawa ,  Katsuaki Natori ,  Takashi Nakao

发明人： Katsuyuki SEKINE ,  Daisuke Nishida ,  Ryota Fujitsuka ,  Yoshio Ozawa ,  Katsuaki Natori ,  Takashi Nakao

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L29/4234 ,  H01L29/7887

摘要： A semiconductor device includes a semiconductor substrate, a tunnel insulating film on the semiconductor substrate, a charge storage layer on the tunnel insulating film, a block insulating film on the charge storage layer, and a control gate electrode on the block insulating film, the charge storage layer including a plurality of layers including first and second charge storage layers, the second charge storage layer being provided on a nearest side of the block insulating film, the first charge storage layer being provided between the tunnel insulating film and the second charge storage layer, the second charge storage layer having a higher trap density than the first charge storage layer, the second charge storage layer having a smaller band gap than the first charge storage layer, and the second charge storage layer having a higher permittivity than the first charge storage layer and a silicon nitride film.

摘要翻译： 半导体器件包括半导体衬底，半导体衬底上的隧道绝缘膜，隧道绝缘膜上的电荷存储层，电荷存储层上的块绝缘膜和块绝缘膜上的控制栅电极，电荷 存储层，包括包括第一和第二电荷存储层的多个层，所述第二电荷存储层设置在所述块绝缘膜的最近侧，所述第一电荷存储层设置在所述隧道绝缘膜和所述第二电荷存储层之间 所述第二电荷存储层具有比所述第一电荷存储层高的陷阱密度，所述第二电荷存储层具有比所述第一电荷存储层更小的带隙，并且所述第二电荷存储层具有比所述第一电荷存储层高的介电常数 层和氮化硅膜。

公开(公告)号：US07651930B2

公开(公告)日：2010-01-26

申请号：US12146802

申请日：2008-06-26

申请人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

发明人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

IPC分类号： H01L21/20

CPC分类号： H01L27/115 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203 ,  H01L29/66825

摘要： A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

摘要翻译： 一种制造半导体存储装置的方法包括在形成在硅衬底上的绝缘膜中的多个位置提供开口部分，然后在其中形成开口部分的绝缘膜上形成非晶硅膜，并且在 开口部。 然后，形成沟槽，将相邻的开口部之间的中点附近的非晶硅膜分割成一个开口部侧的一部分和另一个开口部侧的一部分。 接着，对其中形成沟槽的非晶硅膜进行退火并进行固相结晶以形成具有用作晶种的开口部分的单晶，从而形成硅单晶层。 然后，在硅单晶层上形成存储单元阵列。

公开(公告)号：US20100112791A1

公开(公告)日：2010-05-06

申请号：US12646563

申请日：2009-12-23

申请人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

发明人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

IPC分类号： H01L21/20

CPC分类号： H01L27/115 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203 ,  H01L29/66825

摘要： A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

摘要翻译： 一种制造半导体存储装置的方法包括在形成在硅衬底上的绝缘膜中的多个位置提供开口部分，然后在其中形成开口部分的绝缘膜上形成非晶硅膜，并且在 开口部。 然后，形成沟槽，将相邻的开口部之间的中点附近的非晶硅膜分割成一个开口部侧的一部分和另一个开口部侧的一部分。 接着，对其中形成沟槽的非晶硅膜进行退火并进行固相结晶以形成具有用作晶种的开口部分的单晶，从而形成硅单晶层。 然后，在硅单晶层上形成存储单元阵列。

公开(公告)号：US20090004833A1

公开(公告)日：2009-01-01

申请号：US12146802

申请日：2008-06-26

申请人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

发明人： Takashi Suzuki ,  Hirokazu Ishida ,  Ichiro Mizushima ,  Yoshio Ozawa ,  Fumiki Aiso ,  Katsuyuki Sekine ,  Takashi Nakao ,  Yoshihiko Saito

IPC分类号： H01L21/20

CPC分类号： H01L27/115 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/1203 ,  H01L29/66825

摘要： A method of manufacturing a semiconductor storage device includes providing an opening portion in a plurality of positions in an insulating film formed on a silicon substrate, and thereafter forming an amorphous silicon film on the insulating film, in which the opening portions are formed, and in the opening portions. Then, trenches are formed to divide the amorphous silicon film, in the vicinity of a midpoint between adjacent opening portions, into a portion on one opening portion side and a portion on the other opening portion side. Next, the amorphous silicon film, in which the trenches are formed, is annealed and subjected to solid-phase crystallization to form a single crystal with the opening portions used as seeds, and thereby a silicon single-crystal layer is formed. Then, a memory cell array is formed on the silicon single-crystal layer.

摘要翻译： 一种制造半导体存储装置的方法包括在形成在硅衬底上的绝缘膜中的多个位置提供开口部分，然后在其中形成开口部分的绝缘膜上形成非晶硅膜，并且在 开口部。 然后，形成沟槽，将相邻的开口部之间的中点附近的非晶硅膜分割成一个开口部侧的一部分和另一个开口部侧的一部分。 接着，对其中形成沟槽的非晶硅膜进行退火并进行固相结晶以形成具有用作晶种的开口部分的单晶，从而形成硅单晶层。 然后，在硅单晶层上形成存储单元阵列。

公开(公告)号：US08338875B2

公开(公告)日：2012-12-25

申请号：US12467717

申请日：2009-05-18

申请人： Takashi Nakao

发明人： Takashi Nakao

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/76232

摘要： Isolation trenches are formed in the main surface of a semiconductor substrate, and isolation regions. are embedded in these trenches. First insulating films, charge storage layers, a second insulating film, and a control gate are formed on the main surface of the semiconductor substrate sectioned by the isolation regions. Shielding layers are arranged in the isolation regions in such a manner that their bottom portions are lower than the channel regions and their upper portions are higher than at least the main surface of the semiconductor substrate to provide an electric and magnetic shield between their storage layers and channel regions of adjacent memory cells.

摘要翻译： 隔离沟形成在半导体衬底的主表面和隔离区中。 嵌入这些沟槽。 在由隔离区域分割的半导体衬底的主表面上形成有第一绝缘膜，电荷存储层，第二绝缘膜和控制栅极。 屏蔽层以这样的方式设置在隔离区域中，使得它们的底部低于沟道区域，并且它们的上部比至少半导体衬底的主表面高，以在其存储层之间提供电磁屏蔽，并且 相邻存储单元的通道区域。