公开(公告)号：US20100190317A1

公开(公告)日：2010-07-29

申请号：US12691483

申请日：2010-01-21

申请人： Kazuaki IWASAWA ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

发明人： Kazuaki IWASAWA ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

摘要翻译： 半导体器件制造方法在半导体衬底中具有形成元件隔离沟槽，在元件隔离沟槽的内部形成硅化合物膜，以便嵌入元件隔离沟槽，在第一温度下进行第一氧化处理以使表面 所述硅化合物膜能够通过氧化剂和杂质而不允许含有硅原子的挥发性物质通过的挥发性物质排放防止层，并且在比所述第一温度高的第二温度下进行第二氧化处理 温度以在元件隔离槽内形成被覆氧化硅膜。

公开(公告)号：US20120034754A1

公开(公告)日：2012-02-09

申请号：US13272457

申请日：2011-10-13

申请人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

发明人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

摘要翻译： 半导体器件制造方法在半导体衬底中具有形成元件隔离沟槽，在元件隔离沟槽的内部形成硅化合物膜，以便嵌入元件隔离沟槽，在第一温度下进行第一氧化处理以使表面 所述硅化合物膜能够通过氧化剂和杂质而不允许含有硅原子的挥发性物质通过的挥发性物质排放防止层，并且在比所述第一温度高的第二温度下进行第二氧化处理 温度以在元件隔离槽内形成被覆氧化硅膜。

公开(公告)号：US08080463B2

公开(公告)日：2011-12-20

申请号：US12691483

申请日：2010-01-21

申请人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

发明人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

摘要翻译： 半导体器件制造方法在半导体衬底中具有形成元件隔离沟槽，在元件隔离沟槽的内部形成硅化合物膜，以便嵌入元件隔离沟槽，在第一温度下进行第一氧化处理以使表面 所述硅化合物膜能够通过氧化剂和杂质而不允许含有硅原子的挥发性物质通过的挥发性物质排放防止层，并且在比所述第一温度高的第二温度下进行第二氧化处理 温度以在元件隔离槽内形成被覆氧化硅膜。

公开(公告)号：US20100311220A1

公开(公告)日：2010-12-09

申请号：US12730099

申请日：2010-03-23

申请人： Shogo MATSUO ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Kazuaki Iwasawa

发明人： Shogo MATSUO ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Kazuaki Iwasawa

IPC分类号： H01L21/762

CPC分类号： H01L21/76229 ,  H01L21/02164 ,  H01L21/02323 ,  H01L21/02343 ,  H01L21/3081 ,  H01L21/3124 ,  H01L21/3125 ,  H01L21/316 ,  H01L27/11531 ,  H01L27/11543 ,  H01L27/11548

摘要： A method for manufacturing semiconductor device has forming a plurality of trenches having at least two kinds of aspect ratios on a semiconductor substrate, filling the plurality of trenches with a coating material containing silicon, forming a mask on the coating material in a part of the trenches among the plurality of trenches filled with the coating material, implanting an ion for accelerating oxidation of the coating material into the coating material in the trenches on which the mask is not formed, forming a first insulating film by oxidizing the coating materials into which the ion is implanted, removing the coating material from the part of the trenches after removing the mask and forming a second insulating film in the part of the trenches from which the coating material is removed.

摘要翻译： 半导体器件的制造方法在半导体衬底上形成具有至少两种纵横比的多个沟槽，用包含硅的涂层材料填充多个沟槽，在沟槽的一部分中在涂层材料上形成掩模 在填充有涂层材料的多个沟槽中，将用于加速氧化涂层材料的离子注入到未形成掩模的沟槽中的涂层材料中，通过氧化其中离子的涂层材料形成第一绝缘膜 在移除掩模之后从沟槽的一部分去除涂层材料，并在去除涂层材料的沟槽部分中形成第二绝缘膜。

公开(公告)号：US08329553B2

公开(公告)日：2012-12-11

申请号：US12730099

申请日：2010-03-23

申请人： Shogo Matsuo ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Kazuaki Iwasawa

发明人： Shogo Matsuo ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Kazuaki Iwasawa

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/02164 ,  H01L21/02323 ,  H01L21/02343 ,  H01L21/3081 ,  H01L21/3124 ,  H01L21/3125 ,  H01L21/316 ,  H01L27/11531 ,  H01L27/11543 ,  H01L27/11548

摘要： A method for manufacturing semiconductor device has forming a plurality of trenches having at least two kinds of aspect ratios on a semiconductor substrate, filling the plurality of trenches with a coating material containing silicon, forming a mask on the coating material in a part of the trenches among the plurality of trenches filled with the coating material, implanting an ion for accelerating oxidation of the coating material into the coating material in the trenches on which the mask is not formed, forming a first insulating film by oxidizing the coating materials into which the ion is implanted, removing the coating material from the part of the trenches after removing the mask and forming a second insulating film in the part of the trenches from which the coating material is removed.

摘要翻译： 半导体器件的制造方法在半导体衬底上形成具有至少两种纵横比的多个沟槽，用包含硅的涂层材料填充多个沟槽，在沟槽的一部分中在涂层材料上形成掩模 在填充有涂层材料的多个沟槽中，将用于加速氧化涂层材料的离子注入到未形成掩模的沟槽中的涂层材料中，通过氧化其中离子的涂层材料形成第一绝缘膜 在移除掩模之后从沟槽的一部分去除涂层材料，并在去除涂层材料的沟槽部分中形成第二绝缘膜。

公开(公告)号：US20080090988A1

公开(公告)日：2008-04-17

申请号：US11905049

申请日：2007-09-27

申请人： Keisuke Nakazawa ,  Katsuhiko Tachibana ,  Takeshi Hoshi ,  Masahiro Kiyotoshi ,  Atsuko Kawasaki ,  Osamu Arisumi

发明人： Keisuke Nakazawa ,  Katsuhiko Tachibana ,  Takeshi Hoshi ,  Masahiro Kiyotoshi ,  Atsuko Kawasaki ,  Osamu Arisumi

IPC分类号： C08G77/12 ,  H01L21/31

CPC分类号： H01L21/3125 ,  C08G77/62 ,  C09D183/16 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02326 ,  H01L21/02337

摘要： A method for handling polysilazane or a polysilazane solution includes synthesizing polysilazane and preparing the polysilazane solution in a first space isolated from outside air. The first space is mainly supplied with air from which amine, basic substance, volatile organic compound and acidic substance are eliminated.

摘要翻译： 聚硅氮烷或聚硅氮烷溶液的处理方法包括合成聚硅氮烷并在与外部空气隔离的第一空间中制备聚硅氮烷溶液。 第一个空间主要供应有空气，从中除去胺，碱性物质，挥发性有机化合物和酸性物质。

公开(公告)号：US07407864B2

公开(公告)日：2008-08-05

申请号：US11175305

申请日：2005-07-07

申请人： Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Keisuke Nakazawa ,  Osamu Arisumi ,  Takeshi Hoshi ,  Katsuhiko Tachibana

发明人： Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Keisuke Nakazawa ,  Osamu Arisumi ,  Takeshi Hoshi ,  Katsuhiko Tachibana

IPC分类号： H01L21/76

CPC分类号： H01L21/3125 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31053 ,  H01L21/316 ,  H01L21/76224

摘要： Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a butanol concentration of 30 ppm or less, and polysilazane perhydride dissolved in the dibutyl ether, subjecting the polysilazane perhydride film to oxidation in an atmosphere containing water vapor to form a silicon dioxide film, and selectively removing the silicon dioxide film to leave the silicon dioxide film in the element isolation trench to form an element isolating insulation film.

摘要翻译： 公开了一种制造半导体器件的方法，包括在半导体衬底中形成元件隔离沟槽，在其上形成元件隔离沟槽的半导体衬底上涂覆聚硅氮烷二次酐溶液以形成聚硅氮烷过渡膜，所述聚硅氮烷过硼酸盐溶液包含二丁基醚 具有30ppm以下的丁醇浓度，溶解在二丁基醚中的聚硅氮烷二烷基化钠，在含有水蒸汽的气氛中使聚硅氮烷二次酐膜氧化，形成二氧化硅膜，选择性地除去二氧化硅膜离开硅 元件隔离沟中的二氧化硅膜形成元件隔离绝缘膜。

公开(公告)号：US20060205165A1

公开(公告)日：2006-09-14

申请号：US11175305

申请日：2005-07-07

申请人： Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Keisuke Nakazawa ,  Osamu Arisumi ,  Takeshi Hoshi ,  Katsuhiko Tachibana

发明人： Atsuko Kawasaki ,  Masahiro Kiyotoshi ,  Keisuke Nakazawa ,  Osamu Arisumi ,  Takeshi Hoshi ,  Katsuhiko Tachibana

IPC分类号： H01L21/76

CPC分类号： H01L21/3125 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/31053 ,  H01L21/316 ,  H01L21/76224

摘要： Disclosed is a method of manufacturing a semiconductor device comprising forming an element isolation trench in a semiconductor substrate, coating a polysilazane perhydride solution on the semiconductor substrate having the element isolation trench formed thereon to form a polysilazane perhydride film, the polysilazane perhydride solution comprising dibutyl ether having a butanol concentration of 30 ppm or less, and polysilazane perhydride dissolved in the dibutyl ether, subjecting the polysilazane perhydride film to oxidation in an atmosphere containing water vapor to form a silicon dioxide film, and selectively removing the silicon dioxide film to leave the silicon dioxide film in the element isolation trench to form an element isolating insulation film.

摘要翻译： 公开了一种制造半导体器件的方法，包括在半导体衬底中形成元件隔离沟槽，在其上形成元件隔离沟槽的半导体衬底上涂覆聚硅氮烷二次酐溶液以形成聚硅氮烷过渡膜，所述聚硅氮烷过硼酸盐溶液包含二丁基醚 具有30ppm以下的丁醇浓度，溶解在二丁基醚中的聚硅氮烷二烷基化钠，在含有水蒸汽的气氛中使聚硅氮烷二次酐膜氧化，形成二氧化硅膜，选择性地除去二氧化硅膜离开硅 元件隔离沟中的二氧化硅膜形成元件隔离绝缘膜。

公开(公告)号：US08835279B2

公开(公告)日：2014-09-16

申请号：US13425592

申请日：2012-03-21

申请人： Keisuke Nakazawa

发明人： Keisuke Nakazawa

IPC分类号： H01L21/28 ,  H01L21/76 ,  H01L21/336 ,  H01L29/76 ,  H01L29/788 ,  H01L21/70 ,  H01L27/115 ,  H01L21/764

CPC分类号： H01L27/11524 ,  H01L21/764

摘要： According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method, a tunnel insulating film and a first conductive film are formed on a semiconductor layer. A trench is formed. A first sacrifice film is buried in the trench. A second sacrifice film having density higher than that of the first sacrifice film is formed on the first sacrifice film in the trench. An insulating film is formed on the first conductive film and the second sacrifice film. A second conductive film is formed on the insulating film. The second sacrifice film is exposed. The first sacrifice film and the second sacrifice film are removed.

摘要翻译： 根据一个实施例，提供一种制造半导体器件的方法。 在该方法中，在半导体层上形成隧道绝缘膜和第一导电膜。 形成沟槽。 第一把牺牲电影埋在沟里。 在沟槽中的第一牺牲膜上形成密度高于第一牺牲膜的第二牺牲膜。 在第一导电膜和第二牺牲膜上形成绝缘膜。 在绝缘膜上形成第二导电膜。 第二件牺牲片暴露出来。 第一牺牲膜和第二牺牲膜被去除。

公开(公告)号：US08659114B2

公开(公告)日：2014-02-25

申请号：US13309730

申请日：2011-12-02

申请人： Keisuke Nakazawa

发明人： Keisuke Nakazawa

IPC分类号： H01L21/70 ,  H01L21/31

CPC分类号： H01L29/7881 ,  H01L21/76224 ,  H01L21/76227 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785

摘要： According to one embodiment, a semiconductor device includes a semiconductor substrate, a trench formed in an element isolating area of the semiconductor substrate, and a silicon oxide film that is embedded in the trench and contains an alkali metal element or alkali earth metal element.

摘要翻译： 根据一个实施例，半导体器件包括半导体衬底，形成在半导体衬底的元件隔离区域中的沟槽和埋入沟槽中并含有碱金属元素或碱土金属元素的氧化硅膜。