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12 条记录 (耗时 0.017 秒)

    Semiconductor device and method of manufacturing the same
    1.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US06433381B1

    公开(公告)日：2002-08-13

    申请号：US09756222

    申请日：2001-01-09

    申请人： Kazuhiro Mizutani ,  Michiari Kawano

    发明人： Kazuhiro Mizutani ,  Michiari Kawano

    IPC分类号： H01L27108

    摘要： There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.

    Semiconductor device and method of manufacturing the same
    2.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06794244B2

    公开(公告)日：2004-09-21

    申请号：US10173595

    申请日：2002-06-19

    申请人： Kazuhiro Mizutani ,  Michiari Kawano

    发明人： Kazuhiro Mizutani ,  Michiari Kawano

    IPC分类号： H01L218242

    CPC分类号： H01L21/76831 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76883 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894

    摘要： There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.

    摘要翻译： 提供了具有COB型DRAM的半导体器件，其包括形成在半导体衬底上的第一绝缘膜，形成在第一区域中的第一绝缘膜中的第一布线沟槽，在第二绝缘膜中形成的第二布线沟槽 区域具有与第一布线沟槽基本相同的深度，埋在第一布线沟槽的下部的第一布线，埋在第一布线沟槽的上部并由不同于第一绝缘膜的材料形成的第二绝缘膜，以及 第二布线由与第二布线沟槽中的第一布线相同的导电材料形成并且形成为比第一布线更厚。 因此，可以提高具有不同膜厚度的位线和布线的图案精度，并且以自对准方式形成在位线之间的通孔形成浅，并且还具有位线和 布线减少。

    Semiconductor device and method for manufacturing the same
    6.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US07241676B2

    公开(公告)日：2007-07-10

    申请号：US10948569

    申请日：2004-09-24

    申请人： Kenichi Watanabe ,  Michiari Kawano

    发明人： Kenichi Watanabe ,  Michiari Kawano

    IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/311

    CPC分类号： H01L21/76843 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76838 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/564 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

    摘要： After formation of a contact pattern on a semiconductor substrate, a first wiring pattern composed of a first barrier metal film and a first conductor pattern is formed on the contact pattern. A moisture-proof ring is formed which has such a structure that an outer peripheral portion, covering a sidewall face on the outer peripheral side of the first conductor pattern, of the first barrier metal film, is in contact at the upper end portion with a barrier metal bottom face portion, covering the bottom face of a via contact portion, of a second barrier metal film. This results in formation of a barrier metal film such as Ta, TiN, or the like, with no discontinuation, in the whole region from the semiconductor substrate to an silicon oxide film being the uppermost layer, thereby improving adhesiveness for prevention of cracks and entry of moisture.

    摘要翻译： 在半导体衬底上形成接触图形之后，在接触图形上形成由第一阻挡金属膜和第一导体图案构成的第一布线图案。 形成防潮环，其具有使第一阻挡金属膜的覆盖第一导体图案的外周侧的侧壁面的外周部与上端部接触的结构， 阻挡金属底面部分，覆盖第二阻挡金属膜的通孔接触部分的底面。 这导致在从半导体衬底到作为最上层的氧化硅膜的整个区域中形成诸如Ta，TiN等的阻挡金属膜，而不会中断，从而提高用于防止裂纹和入口的粘附性 的水分。

    Dynamic random access memory having a stacked fin capacitor with reduced fin thickness
    7.
    发明授权
    Dynamic random access memory having a stacked fin capacitor with reduced fin thickness 失效
    动态随机存取存储器，其具有减小翅片厚度的堆叠鳍式电容器

    公开(公告)号：US5661340A

    公开(公告)日：1997-08-26

    申请号：US141691

    申请日：1993-10-26

    申请人： Taiji Ema ,  Masaaki Higashitani ,  Toshimi Ikeda ,  Michiari Kawano ,  Hiroshi Nomura ,  Masaya Katayama ,  Masahiro Kuwamura

    发明人： Taiji Ema ,  Masaaki Higashitani ,  Toshimi Ikeda ,  Michiari Kawano ,  Hiroshi Nomura ,  Masaya Katayama ,  Masahiro Kuwamura

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L23/02 ,  H01L21/265

    CPC分类号： H01L27/10852 ,  H01L27/10817

    摘要： A method for fabricating a dynamic random access memory comprises the steps of forming a diffusion region in a semiconductor substrate, providing an insulation layer on the semiconductor substrate, forming a contact hole in the insulation layer to expose the diffusion region at the contact hole, depositing a semiconductor layer on the insulation layer in the amorphous state such that the semiconductor layer establishes an intimate contact with the exposed diffusion region via the contact hole, patterning the semiconductor layer to form a capacitor electrode, depositing a dielectric film on the capacitor electrode such that said dielectric film covers the capacitor electrode; and depositing a semiconductor material to form an opposing electrode such that the opposing electrode buries the capacitor electrode underneath while establishing an intimate contact with the dielectric film that covers the capacitor electrode.

    摘要翻译： 一种用于制造动态随机存取存储器的方法，包括以下步骤：在半导体衬底中形成扩散区，在半导体衬底上提供绝缘层，在绝缘层上形成接触孔，露出接触孔处的扩散区，沉积 在绝缘层上形成非晶状态的半导体层，使得半导体层经由接触孔与暴露的扩散区域形成紧密接触，构图半导体层以形成电容器电极，在电容器电极上沉积电介质膜，使得 所述电介质膜覆盖电容器电极; 以及沉积半导体材料以形成相对的电极，使得相对电极将电容器电极埋在下面，同时与覆盖电容器电极的电介质膜形成紧密接触。

    Semiconductor device with a wiring layer having good step coverage for contact holes
    8.
    发明授权
    Semiconductor device with a wiring layer having good step coverage for contact holes 失效
    具有布线层的半导体器件具有良好的接触孔阶梯覆盖

    公开(公告)号：US4833519A

    公开(公告)日：1989-05-23

    申请号：US049917

    申请日：1987-05-15

    申请人： Michiari Kawano ,  Masayuki Higashimoto ,  Shigeo Kashiwagi ,  Jun Nakano ,  Osamu Shimizu

    发明人： Michiari Kawano ,  Masayuki Higashimoto ,  Shigeo Kashiwagi ,  Jun Nakano ,  Osamu Shimizu

    IPC分类号： H01L21/285 ,  H01L21/768

    CPC分类号： H01L21/76877 ,  H01L21/28525 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76847 ,  H01L21/76849

    摘要： A method and apparatus are disclosed for improving step coverage of a wiring layer of a semiconductor device especially at the contact holes thereof. The inside of the contact holes are covered by a polysilicon layer deposited by chemical vapor deposition (CVD), and selectively doped with impurities having the same conductivity type as the contact region which the polysilicon layer contacts at the bottom of the contact hole. The remaining part of the contact hole is buried with SiO.sub.2, and the wiring layer is formed on it. Since the step coverage of the material deposited by CVD is very good, the disconnection at the side walls of the contact hole is avoided. Further, short circuits caused by growth of spikes of eutectic of silicon and aluminum is also avoided. If the surface of the polysilicon layer is covered with a thin film of SiO.sub.2 or Si.sub.3 N.sub.4, the material to bury the contact hole may be replaced by other materials such as polysilicon or amorphous silicon. Further, a barrier layer may be provided between the wiring layer and the polysilicon layer. This prevents the migration of aluminum over the polysilicon, so that the reliability of the wiring is further improved. The barrier layer is made from a silicide of high melting point metal or the metal itself. This improves the conduction between the contact region and the wiring layer.