公开(公告)号：US07023061B2

公开(公告)日：2006-04-04

申请号：US11072505

申请日：2005-03-07

申请人： Kazumasa Nomoto ,  Toshio Kobayashi ,  Akihiro Nakamura ,  Ichiro Fujiwara ,  Toshio Terano

发明人： Kazumasa Nomoto ,  Toshio Kobayashi ,  Akihiro Nakamura ,  Ichiro Fujiwara ,  Toshio Terano

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/2815 ,  H01L27/115 ,  H01L29/6656

摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

摘要翻译： 一种半导体器件，其能够以近似的间隔布置字线，包括排列成阵列的多个存储晶体管，以及同时作为沿行方向延伸的同一行中的存储晶体管的栅电极的多条字线，并重复 在列方向上，在多个字线之间形成绝缘膜以使字线彼此绝缘和隔离，并且字线分隔的尺寸由绝缘膜的厚度限定。

公开(公告)号：US06885060B2

公开(公告)日：2005-04-26

申请号：US10101191

申请日：2002-03-19

申请人： Kazumasa Nomoto ,  Toshio Kobayashi

发明人： Kazumasa Nomoto ,  Toshio Kobayashi

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/00

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

摘要： A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

摘要翻译： 一种非易失性半导体存储器件，包括在其表面上具有台阶的第一导电半导体区，形成在每个台阶的上部和底部上的第二导电半导体区域，并且沿垂直于主表面的方向分离 用作源极或漏极的第一导电半导体，其中包含电荷存储装置的栅极电介质膜，空间上离散并形成在第一导电半导体上，以便涂覆至少每一个步骤的侧壁，以及 栅电极形成在栅极电介质膜上。 因此，提供了几乎不会劣化的性能的非易失性半导体存储器件，并且即使当半导体衬底中的半导体存储器件的尺寸缩小时也可以执行每单位存储器件的2位的记录操作 ，以及用于制造非易失性半导体存储器件的工艺。

公开(公告)号：US07049655B2

公开(公告)日：2006-05-23

申请号：US11093376

申请日：2005-03-30

申请人： Kazumasa Nomoto ,  Toshio Kobayashi

发明人： Kazumasa Nomoto ,  Toshio Kobayashi

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

摘要： A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

公开(公告)号：US07034356B2

公开(公告)日：2006-04-25

申请号：US11094680

申请日：2005-03-30

申请人： Kazumasa Nomoto ,  Toshio Kobayashi

发明人： Kazumasa Nomoto ,  Toshio Kobayashi

IPC分类号： H01L23/788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

摘要： A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

公开(公告)号：US20050218522A1

公开(公告)日：2005-10-06

申请号：US11098501

申请日：2005-04-05

申请人： Kazumasa Nomoto ,  Toshio Kobayashi ,  Akihiro Nakamura ,  Ichiro Fujiwara ,  Toshio Terano

发明人： Kazumasa Nomoto ,  Toshio Kobayashi ,  Akihiro Nakamura ,  Ichiro Fujiwara ,  Toshio Terano

IPC分类号： H01L21/28 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/8242

CPC分类号： H01L27/11568 ,  H01L21/2815 ,  H01L27/115 ,  H01L29/6656

摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

公开(公告)号：US20050167735A1

公开(公告)日：2005-08-04

申请号：US11093376

申请日：2005-03-30

申请人： Kazumasa Nomoto ,  Toshio Kobayashi

发明人： Kazumasa Nomoto ,  Toshio Kobayashi

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

摘要： A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

公开(公告)号：US20050146015A1

公开(公告)日：2005-07-07

申请号：US11072505

申请日：2005-03-07

申请人： Kazumasa Nomoto ,  Toshio Kobayashi ,  Akihiro Nakamura ,  Ichiro Fujiwara ,  Toshio Terano

发明人： Kazumasa Nomoto ,  Toshio Kobayashi ,  Akihiro Nakamura ,  Ichiro Fujiwara ,  Toshio Terano

IPC分类号： H01L21/28 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/2815 ,  H01L27/115 ,  H01L29/6656

摘要： A semiconductor device enabling word lines to be arranged at close intervals, comprising a plurality of memory transistors arranged in an array and a plurality of word lines serving also as gate electrodes of memory transistors in a same row, extending in a row direction, and repeating in a column direction, where insulating films are formed between the plurality of word lines to insulate and isolate the word lines from each other and where a dimension of separation of word lines is defined by the thickness of the insulating films.

公开(公告)号：US20050145898A1

公开(公告)日：2005-07-07

申请号：US11043671

申请日：2005-01-26

申请人： Kazumasa Nomoto ,  Toshio Kobayashi

发明人： Kazumasa Nomoto ,  Toshio Kobayashi

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

摘要： A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

公开(公告)号：US07074675B2

公开(公告)日：2006-07-11

申请号：US11043671

申请日：2005-01-26

申请人： Kazumasa Nomoto ,  Toshio Kobayashi

发明人： Kazumasa Nomoto ,  Toshio Kobayashi

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

摘要： A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.

公开(公告)号：US07057233B2

公开(公告)日：2006-06-06

申请号：US11093377

申请日：2005-03-30

申请人： Kazumasa Nomoto ,  Toshio Kobayashi

发明人： Kazumasa Nomoto ,  Toshio Kobayashi

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792 ,  Y10S438/954

摘要： A non-volatile semiconductor memory device comprising a first conductive semiconductor having steps on a surface thereof, a second conductive semiconductor region formed on an upper portion and a bottom portion of each of the steps and being separated in a direction perpendicular to the main surface of the first conductive semiconductor to function as a source or a drain, a gate dielectric film containing therein charge storage means which is spatially discrete and being formed on the first conductive semiconductor so as to coat at least a sidewall of each of the steps, and a gate electrode formed on the gate dielectric film. Accordingly, there are provided a non-volatile semiconductor memory device which suffers almost no deterioration in the properties and can perform the operation of recording of 2 bits per unit memory device even when the size of the semiconductor memory device in the semiconductor substrate is scaled down, and a process for fabricating the non-volatile semiconductor memory device.