公开(公告)号：US4954947A

公开(公告)日：1990-09-04

申请号：US336741

申请日：1989-03-21

申请人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

发明人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

IPC分类号： G06F9/38

CPC分类号： G06F9/3824

摘要： An instruction processor effecting operations for register operands and for processing branch instructions to perform address calculations for branch destination instructions, comprising general-purpose registers storing data including results of operations of said instruction processor, address adders calculating the address of branch destination instructions by using data read out from the general-purpose register and an ALU performing arithmetical or logical operations on the data read out from the general-purpose register in the decode cycle of the instructions. The result of the arithmetical or logical operation is inputted into the address adder but not from the general-purpose register, in the case where the result of the arithmetical or logical operation is utilized for address calculation in the execution of a succeeding instruction.

摘要翻译： 指令处理器对寄存器操作数进行操作并处理分支指令以执行分支目的地指令的地址计算，包括通用寄存器，其存储包括所述指令处理器的操作结果的数据，地址加法器通过使用数据计算分支目的地指令的地址 从通用寄存器读出，以及ALU对指令的解码周期中从通用寄存器读出的数据执行算术或逻辑运算。 在执行后续指令时，算术运算或逻辑运算的结果被用于地址计算的情况下，将算术或逻辑运算的结果输入到地址加法器而不是通用寄存器。

公开(公告)号：US4924377A

公开(公告)日：1990-05-08

申请号：US687161

申请日：1984-12-28

申请人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

发明人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

IPC分类号： G06F9/34 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38

CPC分类号： G06F9/355 ,  G06F9/345 ,  G06F9/383

摘要： Address calculation adders and a buffer storages are each independently provided for each operand of an instruction requiring two or more operands. In the translation instruction processing, the address calculations and operand fetch operations on the first and second operands are substantially asynchronously conducted. Consequently, the overhead that takes place one every n second operand fetch operations can be removed by independently and asynchronously performing the address calculations and operand fetch operations by use of a plurality of address adders. Moreover, the circuit for separating and obtaining a byte from the operand buffer can be dispensed with by adopting an operation procedure in which a byte of the first operand is fetched and is stored in temporary store means that supplies the address adder the data stored therein.

摘要翻译： 对于需要两个或多个操作数的指令的每个操作数，地址计算加法器和缓冲存储器都是独立提供的。 在转换指令处理中，对第一和第二操作数的地址计算和操作数获取操作基本上异步进行。 因此，可以通过使用多个地址加法器独立地和异步地执行地址计算和操作数获取操作来移除每n个第二操作数获取操作发生一次的开销。 此外，可以通过采用其中获取第一操作数的字节的操作过程来存储用于从操作数缓冲器分离和获得字节的电路，并将其存储在向地址加法器提供其中存储的数据的临时存储装置中。

公开(公告)号：US4916606A

公开(公告)日：1990-04-10

申请号：US75528

申请日：1987-07-20

申请人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama ,  Yooichi Shintani

发明人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama ,  Yooichi Shintani

IPC分类号： G06F9/38

CPC分类号： G06F9/3889 ,  G06F9/3824

摘要： A data processing apparatus of processing first instruction of a type in which the result of operation of the first instruction is stored in at least one storage location designated by operands of the first instruction and second instruction of a type which succeeds to the first instruction and makes use of the result of operation of the first instruction as operand data. The apparatus comprises an OSC control circuit for detecting whether at least a part of the result of operation of the first instruction is to be used or not as the operand data for the second instruction, and an arithmetic unit for allowing the result of operation of the first instruction to be directly used as the operand data for the second instruction when the OSC control circuit detects the given condition is fulfilled.

摘要翻译： 一种处理第一指令的第一指令的数据处理装置，其中第一指令的操作结果被存储在由第一指令的操作数指定的至少一个存储位置中，并且第二指令成为第一指令成功的类型 使用第一条指令的操作结果作为操作数据。 该装置包括用于检测是否要使用第一指令的操作结果的至少一部分作为第二指令的操作数数据的OSC控制电路，以及用于允许第二指令的操作结果的运算单元 当OSC控制电路检测到给定条件时，直接用作第二指令的操作数数据的第一指令被满足。

公开(公告)号：US4745569A

公开(公告)日：1988-05-17

申请号：US686692

申请日：1984-12-27

申请人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama

发明人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama

IPC分类号： G06F7/496 ,  G06F7/491 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527

CPC分类号： G06F7/4915

摘要： A decimal multiplier device including a register A storing the multiplier, a register B storing the multiplicand, a shifter for outputting the output of the register A as it is or after having been shifted, based on a first signal, a gate for outputting the output of the register B or "0", based on a second signal, an adder/subtractor for adding the output of the shifter and that of the gate and storing the result thus obtained in the register A, and a decoder for receiving the value of a selected digit of the content of the register A and controlling the gate and the shifter by generating the first signal and the second signal based on the received value so that the multiplicand B is added n times, n corresponding to the received value, to the content of the register A or substracted (10-n) times therefrom. The register A, the shifter and the adder/subtractor form a single loop. Decimal multiplication is performed by controlling the shifter, when signals pass through the loop repeatedly.

摘要翻译： 十进制乘法器装置，包括存储乘法器的寄存器A，存储被乘数的寄存器B，用于根据第一信号输出寄存器A的输出或移位后的移位器，用于输出输出的门 的寄存器B或“0”，基于第二信号的加法器/减法器，用于将移位器的输出和门的输出相加并存储在寄存器A中的结果;以及解码器，用于接收 所选择的寄存器A的内容的数字，并且通过基于接收的值产生第一信号和第二信号来控制门和移位器，使得被乘数B与被接收的值相对应的n次，n对应于接收的值 寄存器A的内容或从其减去（10-n）倍。 寄存器A，移位器和加法器/减法器形成单个循环。 当信号反复通过环路时，通过控制移位器执行十进制乘法。

公开(公告)号：US4692891A

公开(公告)日：1987-09-08

申请号：US668842

申请日：1984-11-06

申请人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama

发明人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama

IPC分类号： G06F7/496 ,  G06F7/491 ,  G06F7/493 ,  G06F7/508 ,  G06F7/52 ,  G06F7/535 ,  G06F7/537

CPC分类号： G06F7/4917

摘要： This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division.A dividend is stored in a register B and a divisor, in a register C. A selector 6 selects register B when the result of subtraction by an adder/subtracter 1 is positive or zero, and selects register A at other times. Both adder/subtracter 1 and a shifter 2 receive the signal from the selector 6 in the same way, and execute the subtraction processing and the shift processing, respectively. The results of these processings are stored in the registers B and A', respectively.The division time can be shortened because the adder/subtracter 1 and the shifter 2 can be actuated simultaneously.

摘要翻译： 本发明采用并行执行十进制除法中的减法处理和数位移位处理以缩短小数除法所需的时间的结构。 在寄存器C中将寄存器B和除数存储除数。当加法器/减法器1的减法结果为正或0时，选择器6选择寄存器B，并且在其他时间选择寄存器A. 加法器/减法器1和移位器2以相同的方式接收来自选择器6的信号，并分别执行减法处理和移位处理。 这些处理的结果分别存储在寄存器B和A'中。 由于可以同时启动加法器/减法器1和移位器2，所以可以缩短分频时间。

公开(公告)号：US4758949A

公开(公告)日：1988-07-19

申请号：US928055

申请日：1986-11-07

申请人： Kenichi Wada ,  Kazunori Kuriyama ,  Akira Yamaoka

发明人： Kenichi Wada ,  Kazunori Kuriyama ,  Akira Yamaoka

IPC分类号： G06F9/38

CPC分类号： G06F9/3873 ,  G06F9/3802 ,  G06F9/3836

摘要： An information processing apparatus having a buffer register for pre-fetching a plurality of instructions and executing one instruction after another by reading them from the buffer registers, is provided with a first instruction decode start determination unit for register type instructions and a second instruction decode start determination unit for non-register type instructions, provided separately from the first unit, whereby 0.5 cycle after a register type instruction starts being decoded, or 1 cycle after a non-register type instruction starts being decoded, the next instruction starts to be decoded. By decoding a register type instruction at high speed, it becomes possible to execute a branch instruction at high speed.

摘要翻译： 具有用于预取多个指令并且通过从缓冲寄存器读取它们来执行一个指令的缓冲寄存器的信息处理装置设置有用于寄存器类型指令的第一指令解码开始确定单元和第二指令解码开始 与第一单元分开设置的非寄存器类型指令的确定单元，其中在寄存器类型指令开始被解码之后的0.5个周期，或者在非寄存器类型指令开始被解码之后的1个周期，下一个指令开始被解码。 通过高速解码寄存器类型指令，可以高速执行分支指令。

公开(公告)号：US5201040A

公开(公告)日：1993-04-06

申请号：US209073

申请日：1988-06-20

申请人： Kenichi Wada ,  Akira Yamaoka

发明人： Kenichi Wada ,  Akira Yamaoka

IPC分类号： G06F15/17

CPC分类号： G06F15/17

摘要： A data processing system which has a plurality of sets of sub-systems, with each set including: a plurality of processors; a main storage; and a controller for controlling the transfer between at least each of the processors and the main storage. A shared storage apparatus is shared between the sub-systems to store exclusive control information, information on the processor-to-processor communications and an instruction to be transferred between the main storages and the shared storage apparatus when the information is accessed by each sub-system. The instruction designates a main storage address, a transfer data length and specified information on accessing the location of the shared storage apparatus and is decoded by the processors to that the main storage address is transferred to the main storage, whereas the specified information such as a data identifier and a relative address is transferred to the shared storage apparatus.

摘要翻译： 一种具有多组子系统的数据处理系统，每组包括：多个处理器; 主要存储; 以及用于控制至少每个处理器和主存储器之间的传送的控制器。 在每个子系统访问信息时，在子系统之间共享共享存储装置以存储专用控制信息，关于处理器到处理器通信的信息和要在主存储器和共享存储装置之间传送的指令， 系统。 该指令指定主存储地址，传输数据长度和关于访问共享存储设备的位置的指定信息，并且被处理器解码为主存储地址被传送到主存储器，而指定的信息例如 数据标识符和相对地址被传送到共享存储装置。

公开(公告)号：US4739470A

公开(公告)日：1988-04-19

申请号：US489349

申请日：1983-04-28

申请人： Kenichi Wada ,  Yooichi Shintani ,  Tsuguo Shimizu ,  Akira Yamaoka

发明人： Kenichi Wada ,  Yooichi Shintani ,  Tsuguo Shimizu ,  Akira Yamaoka

IPC分类号： G06F9/38

CPC分类号： G06F9/3889 ,  G06F9/383

摘要： A data processing system for executing an instruction in a plurality of stages in a pipeline mode comprises a main operation unit capable of executing all instructions to be executed in the data processing system, a pre-operation unit capable of executing instructions which occurs at a high frequency and can be executed with a small number of circuit components, general purpose registers for storing operation results of the instructions, and a control unit for controlling the writing of the operation results by the main operation unit and the pre-operation unit into the general purpose registers.

摘要翻译： 一种用于在流水线模式中执行多级指令的数据处理系统，包括能够执行在数据处理系统中执行的所有指令的主操作单元，能够执行高位指令的预操作单元 并且可以用少量的电路部件执行，用于存储指令的操作结果的通用寄存器，以及用于控制主操作单元和预操作单元的操作结果写入一般的控制单元 目的寄存器。

公开(公告)号：US4608671A

公开(公告)日：1986-08-26

申请号：US490518

申请日：1983-05-02

申请人： Tsuguo Shimizu ,  Kenichi Wada ,  Yooichi Shintani ,  Akira Yamaoka

发明人： Tsuguo Shimizu ,  Kenichi Wada ,  Yooichi Shintani ,  Akira Yamaoka

IPC分类号： G06F12/08 ,  G06F12/12 ,  G11C8/00

CPC分类号： G06F12/128

摘要： In a buffer storage device where swapping of data is employed, plural candidates for replacement of data in a buffer are determined in response to any access to the buffer storage, and, when the replacement is required, one of the candidates is selected so that processing time for replacement can be minimum.

摘要翻译： 在采用交换数据的缓冲存储装置中，响应于对缓冲存储器的任何访问来确定用于替换缓冲器中的数据的多个候选，并且当需要更换时，选择候选中的一个，使得处理 更换时间可以是最少的。

公开(公告)号：US4532589A

公开(公告)日：1985-07-30

申请号：US446002

申请日：1982-12-01

申请人： Yoichi Shintani ,  Kenichi Wada ,  Tsuguo Shimizu ,  Akira Yamaoka

发明人： Yoichi Shintani ,  Kenichi Wada ,  Tsuguo Shimizu ,  Akira Yamaoka

IPC分类号： G06F9/38 ,  G06F9/00

CPC分类号： G06F9/3889 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3885

摘要： In a data processing apparatus executing a plurality of instructions in a pipeline mode by dividing each of the instructions into a plurality of stages, its operation circuit includes a first execution (E) unit capable of execution of operations required by all of the plural instructions and a second E unit capable of execution of operations required by part of the plural instructions only. A queue of data including decoded information of the instructions required for execution of operation stages are stored in a circuit to be selectively supplied by first and second circuits to the first and second E units, respectively. The first and second circuits sequentially select succeeding data in synchronism with the end of operations in the first and second E units respectively. As a result, when a stage of a succeeding instruction requires the result of operation of a preceding instruction being executed, that stage of the succeeding instruction is executed after the second E unit completes the operation of the preceding instruction, even when the first E unit is executing an instruction further preceding the preceding instruction.

摘要翻译： 在通过将每个指令分成多个级来执行流水线模式的多个指令的数据处理装置中，其操作电路包括能够执行所有多个指令所需的操作的第一执行（E）单元，以及 能够执行多个指令的一部分所需的操作的第二E单元。 包括执行操作阶段所需指令的解码信息的数据队列被存储在电路中，以分别由第一和第二电路选择性地提供给第一和第二E单元。 第一和第二电路分别顺序地选择与第一和第二E单元中的操作结束同步的后续数据。 结果，当后续指令的阶段需要执行前一指令的操作结果时，即使在第一E单元完成了第二E单元完成前一指令的操作之后，执行后续指令的该阶段 正在执行进一步在前面的指令之前的指令。