公开(公告)号：US4924377A

公开(公告)日：1990-05-08

申请号：US687161

申请日：1984-12-28

申请人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

发明人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

IPC分类号： G06F9/34 ,  G06F9/345 ,  G06F9/355 ,  G06F9/38

CPC分类号： G06F9/355 ,  G06F9/345 ,  G06F9/383

摘要： Address calculation adders and a buffer storages are each independently provided for each operand of an instruction requiring two or more operands. In the translation instruction processing, the address calculations and operand fetch operations on the first and second operands are substantially asynchronously conducted. Consequently, the overhead that takes place one every n second operand fetch operations can be removed by independently and asynchronously performing the address calculations and operand fetch operations by use of a plurality of address adders. Moreover, the circuit for separating and obtaining a byte from the operand buffer can be dispensed with by adopting an operation procedure in which a byte of the first operand is fetched and is stored in temporary store means that supplies the address adder the data stored therein.

摘要翻译： 对于需要两个或多个操作数的指令的每个操作数，地址计算加法器和缓冲存储器都是独立提供的。 在转换指令处理中，对第一和第二操作数的地址计算和操作数获取操作基本上异步进行。 因此，可以通过使用多个地址加法器独立地和异步地执行地址计算和操作数获取操作来移除每n个第二操作数获取操作发生一次的开销。 此外，可以通过采用其中获取第一操作数的字节的操作过程来存储用于从操作数缓冲器分离和获得字节的电路，并将其存储在向地址加法器提供其中存储的数据的临时存储装置中。

公开(公告)号：US4758949A

公开(公告)日：1988-07-19

申请号：US928055

申请日：1986-11-07

申请人： Kenichi Wada ,  Kazunori Kuriyama ,  Akira Yamaoka

发明人： Kenichi Wada ,  Kazunori Kuriyama ,  Akira Yamaoka

IPC分类号： G06F9/38

CPC分类号： G06F9/3873 ,  G06F9/3802 ,  G06F9/3836

摘要： An information processing apparatus having a buffer register for pre-fetching a plurality of instructions and executing one instruction after another by reading them from the buffer registers, is provided with a first instruction decode start determination unit for register type instructions and a second instruction decode start determination unit for non-register type instructions, provided separately from the first unit, whereby 0.5 cycle after a register type instruction starts being decoded, or 1 cycle after a non-register type instruction starts being decoded, the next instruction starts to be decoded. By decoding a register type instruction at high speed, it becomes possible to execute a branch instruction at high speed.

摘要翻译： 具有用于预取多个指令并且通过从缓冲寄存器读取它们来执行一个指令的缓冲寄存器的信息处理装置设置有用于寄存器类型指令的第一指令解码开始确定单元和第二指令解码开始 与第一单元分开设置的非寄存器类型指令的确定单元，其中在寄存器类型指令开始被解码之后的0.5个周期，或者在非寄存器类型指令开始被解码之后的1个周期，下一个指令开始被解码。 通过高速解码寄存器类型指令，可以高速执行分支指令。

公开(公告)号：US4954947A

公开(公告)日：1990-09-04

申请号：US336741

申请日：1989-03-21

申请人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

发明人： Kazunori Kuriyama ,  Kenichi Wada ,  Akira Yamaoka

IPC分类号： G06F9/38

CPC分类号： G06F9/3824

摘要： An instruction processor effecting operations for register operands and for processing branch instructions to perform address calculations for branch destination instructions, comprising general-purpose registers storing data including results of operations of said instruction processor, address adders calculating the address of branch destination instructions by using data read out from the general-purpose register and an ALU performing arithmetical or logical operations on the data read out from the general-purpose register in the decode cycle of the instructions. The result of the arithmetical or logical operation is inputted into the address adder but not from the general-purpose register, in the case where the result of the arithmetical or logical operation is utilized for address calculation in the execution of a succeeding instruction.

摘要翻译： 指令处理器对寄存器操作数进行操作并处理分支指令以执行分支目的地指令的地址计算，包括通用寄存器，其存储包括所述指令处理器的操作结果的数据，地址加法器通过使用数据计算分支目的地指令的地址 从通用寄存器读出，以及ALU对指令的解码周期中从通用寄存器读出的数据执行算术或逻辑运算。 在执行后续指令时，算术运算或逻辑运算的结果被用于地址计算的情况下，将算术或逻辑运算的结果输入到地址加法器而不是通用寄存器。

公开(公告)号：US4916606A

公开(公告)日：1990-04-10

申请号：US75528

申请日：1987-07-20

申请人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama ,  Yooichi Shintani

发明人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama ,  Yooichi Shintani

IPC分类号： G06F9/38

CPC分类号： G06F9/3889 ,  G06F9/3824

摘要： A data processing apparatus of processing first instruction of a type in which the result of operation of the first instruction is stored in at least one storage location designated by operands of the first instruction and second instruction of a type which succeeds to the first instruction and makes use of the result of operation of the first instruction as operand data. The apparatus comprises an OSC control circuit for detecting whether at least a part of the result of operation of the first instruction is to be used or not as the operand data for the second instruction, and an arithmetic unit for allowing the result of operation of the first instruction to be directly used as the operand data for the second instruction when the OSC control circuit detects the given condition is fulfilled.

摘要翻译： 一种处理第一指令的第一指令的数据处理装置，其中第一指令的操作结果被存储在由第一指令的操作数指定的至少一个存储位置中，并且第二指令成为第一指令成功的类型 使用第一条指令的操作结果作为操作数据。 该装置包括用于检测是否要使用第一指令的操作结果的至少一部分作为第二指令的操作数数据的OSC控制电路，以及用于允许第二指令的操作结果的运算单元 当OSC控制电路检测到给定条件时，直接用作第二指令的操作数数据的第一指令被满足。

公开(公告)号：US4745569A

公开(公告)日：1988-05-17

申请号：US686692

申请日：1984-12-27

申请人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama

发明人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama

IPC分类号： G06F7/496 ,  G06F7/491 ,  G06F7/508 ,  G06F7/52 ,  G06F7/527

CPC分类号： G06F7/4915

摘要： A decimal multiplier device including a register A storing the multiplier, a register B storing the multiplicand, a shifter for outputting the output of the register A as it is or after having been shifted, based on a first signal, a gate for outputting the output of the register B or "0", based on a second signal, an adder/subtractor for adding the output of the shifter and that of the gate and storing the result thus obtained in the register A, and a decoder for receiving the value of a selected digit of the content of the register A and controlling the gate and the shifter by generating the first signal and the second signal based on the received value so that the multiplicand B is added n times, n corresponding to the received value, to the content of the register A or substracted (10-n) times therefrom. The register A, the shifter and the adder/subtractor form a single loop. Decimal multiplication is performed by controlling the shifter, when signals pass through the loop repeatedly.

摘要翻译： 十进制乘法器装置，包括存储乘法器的寄存器A，存储被乘数的寄存器B，用于根据第一信号输出寄存器A的输出或移位后的移位器，用于输出输出的门 的寄存器B或“0”，基于第二信号的加法器/减法器，用于将移位器的输出和门的输出相加并存储在寄存器A中的结果;以及解码器，用于接收 所选择的寄存器A的内容的数字，并且通过基于接收的值产生第一信号和第二信号来控制门和移位器，使得被乘数B与被接收的值相对应的n次，n对应于接收的值 寄存器A的内容或从其减去（10-n）倍。 寄存器A，移位器和加法器/减法器形成单个循环。 当信号反复通过环路时，通过控制移位器执行十进制乘法。

公开(公告)号：US4692891A

公开(公告)日：1987-09-08

申请号：US668842

申请日：1984-11-06

申请人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama

发明人： Akira Yamaoka ,  Kenichi Wada ,  Kazunori Kuriyama

IPC分类号： G06F7/496 ,  G06F7/491 ,  G06F7/493 ,  G06F7/508 ,  G06F7/52 ,  G06F7/535 ,  G06F7/537

CPC分类号： G06F7/4917

摘要： This invention employs a construction in which subtraction processing and digit shift processing in decimal division are carried out in parallel with each other to shorten the time required for decimal division.A dividend is stored in a register B and a divisor, in a register C. A selector 6 selects register B when the result of subtraction by an adder/subtracter 1 is positive or zero, and selects register A at other times. Both adder/subtracter 1 and a shifter 2 receive the signal from the selector 6 in the same way, and execute the subtraction processing and the shift processing, respectively. The results of these processings are stored in the registers B and A', respectively.The division time can be shortened because the adder/subtracter 1 and the shifter 2 can be actuated simultaneously.

摘要翻译： 本发明采用并行执行十进制除法中的减法处理和数位移位处理以缩短小数除法所需的时间的结构。 在寄存器C中将寄存器B和除数存储除数。当加法器/减法器1的减法结果为正或0时，选择器6选择寄存器B，并且在其他时间选择寄存器A. 加法器/减法器1和移位器2以相同的方式接收来自选择器6的信号，并分别执行减法处理和移位处理。 这些处理的结果分别存储在寄存器B和A'中。 由于可以同时启动加法器/减法器1和移位器2，所以可以缩短分频时间。

公开(公告)号：US4858105A

公开(公告)日：1989-08-15

申请号：US30434

申请日：1987-03-26

申请人： Kazunori Kuriyama ,  Yooichi Shintani ,  Akira Yamaoka ,  Tohru Shonai ,  Eiki Kamada ,  Kiyoshi Inoue

发明人： Kazunori Kuriyama ,  Yooichi Shintani ,  Akira Yamaoka ,  Tohru Shonai ,  Eiki Kamada ,  Kiyoshi Inoue

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/3816 ,  G06F9/30149 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3889

摘要： A pipelined data processor comprises a circuit for storing two instructions in a pair of instruction registers, a circuit for detecting whether those instructions are a combination of an instruction requesting the use of an operation unit and an instruction requesting the use of another resource, and a circuit to control the execution of the instructions when the decision of the detection circuit is affirmative such that those instructions are executed by the operation unit and the resource in a plurality of stages.

摘要翻译： 流水线数据处理器包括用于在一对指令寄存器中存储两个指令的电路，用于检测这些指令是否是请求使用操作单元的指令与请求使用另一资源的指令的组合的电路，以及 电路，用于当检测电路的判定为肯定时控制指令的执行，使得这些指令由操作单元和资源在多个级中执行。

公开(公告)号：US5706465A

公开(公告)日：1998-01-06

申请号：US215109

申请日：1994-03-21

申请人： Hiroshi Kurokawa ,  Kazunori Kuriyama ,  Naohiko Irie

发明人： Hiroshi Kurokawa ,  Kazunori Kuriyama ,  Naohiko Irie

IPC分类号： G06F9/38 ,  G06F12/00 ,  G06F12/08 ,  G06F13/00

CPC分类号： G06F9/3877 ,  G06F12/0888 ,  G06F9/3824

摘要： An auxiliary data processor having an built-in multi-entry data memory is directly connected to a main storage, and executes, directly accessing the main storage, commands sent from a plurality of instruction processors. One data memory entry is assigned to an instruction processor that issued a command, and reserves data fetched from the main storage in response to the command so that the next command can use part of that data. A tag circuit holds an identifier of each instruction processor to which a data memory entry has been assigned and the address and length of data hold in that entry, and see that each command uses the reserved data correctly. Each instruction processor selects commands to be sent to the auxiliary data processor depending upon the conditions of operands. A large amount of data is processed at a high rate, minimizing cache pollution.

摘要翻译： 具有内置多入口数据存储器的辅助数据处理器直接连接到主存储器，并且执行从多个指令处理器发送的命令直接访问主存储器。 一个数据存储器条目被分配给发出命令的指令处理器，并且响应于命令保留从主存储器获取的数据，使得下一个命令可以使用该数据的一部分。 标签电路保存已经分配了数据存储器条目的每个指令处理器的标识符，并且在该条目中保存数据的地址和长度，并且看到每个命令正确地使用保留的数据。 每个指令处理器根据操作数的条件选择要发送到辅助数据处理器的命令。 以高速率处理大量数据，最大限度地减少高速缓存污染。

公开(公告)号：US5075849A

公开(公告)日：1991-12-24

申请号：US292346

申请日：1988-12-30

申请人： Kazunori Kuriyama ,  Yooichi Shintani ,  Tohru Shonai ,  Eiki Kamada ,  Kiyoshi Inoue

发明人： Kazunori Kuriyama ,  Yooichi Shintani ,  Tohru Shonai ,  Eiki Kamada ,  Kiyoshi Inoue

IPC分类号： G06F9/38

CPC分类号： G06F9/3824

摘要： An information processor detects a conflict between successive instructions by determining whether a preceding instruction under execution calls for fetching a first operand from a main memory, generating execution result data based on the first operand and updating one of a plurality of address data designated by a to-be-executed succeeding instruction, with the execution result data. When a conflict is detected, there is supplied to an address adder at least some of the plurality of address data determined by a type of the preceding instruction to complete an operand address calculation stage for the succeeding instruction. Then, before the one address data is updated by the preceding instruction after the first operand has been fetched from the main memory in an operand fetch stage for the preceding instruction, an operation determined by the preceding instruction is performed on the output of the address adder and the fetched first operand to generate an address equal to a sum of the plurality of address data, excluding said one address, and the execution result data for the preceding instruction, and this address is used as the address of the second operand of the succeeding instruction.

摘要翻译： 信息处理器通过确定执行中的前一指令是否从主存储器取出第一操作数，检测基于第一操作数的执行结果数据，并更新由a至 执行后续指令，执行结果数据。 当检测到冲突时，由地址加法器提供由前一条指令的类型确定的多个地址数据中的至少一些，以完成后续指令的操作数地址计算阶段。 然后，在前一条指令的操作数获取级中从主存储器取出第一操作数之前，先前指令更新一个地址数据之前，对地址加法器的输出执行由先前指令确定的操作 以及所取出的第一操作数，以产生等于除所述一个地址之外的多个地址数据之和的地址和前一条指令的执行结果数据，并且该地址被用作后续的第二操作数的地址 指令。

公开(公告)号：US5734918A

公开(公告)日：1998-03-31

申请号：US504600

申请日：1995-07-20

申请人： Hiroaki Odawara ,  Moritoshi Yasunaga ,  Kazunori Kuriyama

发明人： Hiroaki Odawara ,  Moritoshi Yasunaga ,  Kazunori Kuriyama

IPC分类号： G06F13/10 ,  G06F3/06 ,  G06F13/12 ,  H04L29/06 ,  H04L29/08 ,  G06F15/20

CPC分类号： H04L67/06 ,  H04L67/1097 ,  H04L69/16 ,  H04L69/161 ,  H04L69/329

摘要： A data processor transfers files at high speeds from a magnetic disk or other storage media to a network and shortens the processing time for the file transfers. An I/O processor includes (i) a channel to which a magnetic disk is connected, (ii) a LAN adapter to which a network is connected, (iii) a switch for switching and connecting the channel and LAN adapter, and (iv) a channel controller for controlling the channel, the LAN adapter, and the switch. The channel controller controls the channel, the LAN adapter, and the switch in accordance with a data transfer start instruction from an instruction processor. The channel reads data from the magnetic disk and transfers it to the LAN adapter via the switch. The LAN adapter sends the data to the network or reads data from the network and transfers it to the channel via the switch. The channel sends the data to the magnetic disk.

摘要翻译： 数据处理器以高速将文件从磁盘或其他存储介质传输到网络，并缩短文件传输的处理时间。 I / O处理器包括（i）连接磁盘的通道，（ii）连接网络的LAN适配器，（iii）用于切换和连接通道和LAN适配器的开关，以及（iv ）用于控制信道的通道控制器，LAN适配器和开关。 通道控制器根据来自指令处理器的数据传输开始指令控制通道，LAN适配器和开关。 通道从磁盘读取数据，并通过交换机将其传输到LAN适配器。 LAN适配器将数据发送到网络或从网络读取数据，并通过交换机将其传输到通道。 通道将数据发送到磁盘。