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    Picture decoding method and apparatus
    2.
    发明授权
    Picture decoding method and apparatus 失效
    图像解码方法及装置

    公开(公告)号：US06539056B1

    公开(公告)日：2003-03-25

    申请号：US09358451

    申请日：1999-07-21

    申请人： Kazushi Sato ,  Kenji Komori ,  Tetsuo Kaneko ,  Satoshi Mitsuhashi ,  Masami Goseki ,  Takao Terao ,  Naofumi Yanagihara

    发明人： Kazushi Sato ,  Kenji Komori ,  Tetsuo Kaneko ,  Satoshi Mitsuhashi ,  Masami Goseki ,  Takao Terao ,  Naofumi Yanagihara

    IPC分类号： H04N1102

    CPC分类号： H04N19/59 ,  H04N19/117 ,  H04N19/159 ,  H04N19/16 ,  H04N19/186 ,  H04N19/48 ,  H04N19/51 ,  H04N19/523 ,  H04N19/61 ,  H04N19/90

    摘要： An MPEG downdecoder is to be provided which eliminates dephasing of pixels during motion compensation to prevent deterioration of the picture quality ascribable to motion compensation. MPEG data of a high resolution picture are processed by decimating IDCT devices 14, 15 with 4×4 decimating IDCT to decode data of standard resolution picture data. In the case of the field motion prediction mode, a motion compensation device 18 interpolates respective pixels of a macro-block of reference picture data stored in a frame memory 17 to generate a macro-block constituted by pixels of ¼ pixel precision. In the case of the frame motion prediction mode, a motion compensation device 19 interpolates respective pixels of macro-block of reference picture data stored in the frame memory 17 to generate a macro-block constituted by pixels of ¼ pixel precision.

    摘要翻译： 将提供一种在运动补偿期间消除像素的去相位以防止归因于运动补偿的图像质量劣化的MPEG下变频器。 通过用4×4抽取IDCT抽取IDCT设备14,15来处理高分辨率图像的MPEG数据，以对标准分辨率图像数据的数据进行解码。 在场运动预测模式的情况下，运动补偿装置18内插存储在帧存储器17中的参考图像数据的宏块的各个像素，以生成由1/4像素精度的像素构成的宏块。 在帧运动预测模式的情况下，运动补偿装置19内插存储在帧存储器17中的参考图像数据的宏块的各个像素，以生成由1/4像素精度的像素构成的宏块。

    Picture decoding method and apparatus
    3.
    发明授权
    Picture decoding method and apparatus 失效
    图像解码方法及装置

    公开(公告)号：US06580830B1

    公开(公告)日：2003-06-17

    申请号：US09358032

    申请日：1999-07-21

    申请人： Kazushi Sato ,  Kenji Komori ,  Tetsuo Kaneko ,  Satoshi Mitsuhashi ,  Masami Goseki ,  Naofumi Yanagihara

    发明人： Kazushi Sato ,  Kenji Komori ,  Tetsuo Kaneko ,  Satoshi Mitsuhashi ,  Masami Goseki ,  Naofumi Yanagihara

    IPC分类号： G06K936

    CPC分类号： H04N7/014 ,  G06F17/147 ,  H04N7/0125 ,  H04N19/122 ,  H04N19/132 ,  H04N19/157 ,  H04N19/176 ,  H04N19/523 ,  H04N19/59 ,  H04N19/61 ,  H04N19/80 ,  H04N19/90

    摘要： An MPEG downdecoder is to be provided which eliminates dephasing of pixels of moving picture data without losing properties inherent in a picture obtained on interlaced scanning. In the case of a field DCT mode, 4×4 decimating IDCT is executed for phase correction for a ¼ pixel for pixels in the vertical direction of a top field and for phase correction for ¾ pixel for pixels in the vertical direction of a bottom field. In the case of a frame DCT mode, the totality of coefficients of a DCT block are IDCTed and separated into two pixel blocks associated with interlaced scanning. The low-frequency components of these two pixel blocks are IDCTed to synthesize the two pixel blocks. The pixels in the vertical direction of the top field are phase-corrected by a ¼ pixel, while those in the vertical direction of the bottom field are phase-corrected by a ¾ pixel.

    摘要翻译： 将提供一种MPEG降解编码器，其消除了运动图像数据的像素的去相位，而不会损失在隔行扫描中获得的图像中固有的特性。 在场DCT模式的情况下，对顶场的垂直方向上的像素的1/4像素执行4×4抽取IDCT，并且对于底场的垂直方向上的像素的¾像素进行相位校正。 在帧DCT模式的情况下，DCT块的系数的总和被IDCT化并分离成与隔行扫描相关联的两个像素块。 这两个像素块的低频分量被IDCTed以合成两个像素块。 顶场的垂直方向上的像素被1/4像素相位校正，而底场的垂直方向上的像素被¾像素相位校正。

    Picture decoding method and apparatus
    4.
    发明授权
    Picture decoding method and apparatus 失效
    图像解码方法及装置

    公开(公告)号：US06493391B1

    公开(公告)日：2002-12-10

    申请号：US09357895

    申请日：1999-07-21

    申请人： Kenji Komori ,  Tetsuo Kaneko ,  Kazushi Sato ,  Satoshi Mitsuhashi ,  Masami Goseki ,  Naofumi Yanagihara

    发明人： Kenji Komori ,  Tetsuo Kaneko ,  Kazushi Sato ,  Satoshi Mitsuhashi ,  Masami Goseki ,  Naofumi Yanagihara

    IPC分类号： H04B166

    CPC分类号： H04N19/105 ,  H04N19/112 ,  H04N19/137 ,  H04N19/48 ,  H04N19/59 ,  H04N19/90

    摘要： An MPEG downdecoder which eliminates picture quality deterioration ascribable to motion compensation. A decimating inverse discrete cosine transform unit 14 performs 4×4 decimating IDCT if the DCT mode is the field mode. If the DCT mode is the frame mode, a decimating IDCT unit for frame mode 15 applies IDCT to the totality of the coefficients of the DCT block and separates the DCT block into two pixel blocks in order to cope with the interlaced scanning. Each of the separated pixel blocks is processed with DCT. To reference picture data, pixels are interpolated using orthogonal transform by motion compensation units 18, 19 to generate virtual upper-order picture data of high resolution, which is processed with motion compensation. The motion-compensated virtual upper-order picture data is orthogonal transformed to decimate pixels to generate reference picture data used for addition.

    摘要翻译： MPEG downdecoder，可消除归因于运动补偿的图像质量恶化。 如果DCT模式是场模式，则抽取逆离散余弦变换单元14执行4×4抽取IDCT。 如果DCT模式是帧模式，则用于帧模式15的抽取IDCT单元将IDCT应用于DCT块的系数的全部，并将DCT块分离成两个像素块，以便处理隔行扫描。 每个分离的像素块用DCT处理。 为了参考图像数据，使用由运动补偿单元18,19进行的正交变换来内插像素，以生成用运动补偿处理的高分辨率的虚拟高阶图像数据。 运动补偿虚拟高阶图像数据被正交变换以抽取像素以生成用于相加的参考图像数据。

    Inverse discrete-cosine transform apparatus
    5.
    发明授权
    Inverse discrete-cosine transform apparatus 失效
    逆离散余弦变换装置

    公开(公告)号：US06735609B2

    公开(公告)日：2004-05-11

    申请号：US09794296

    申请日：2001-02-27

    申请人： Rajesh Kumar Dixit ,  Takao Terao ,  Hiroshi Sugawara ,  Masami Goseki ,  Kazushi Sato

    发明人： Rajesh Kumar Dixit ,  Takao Terao ,  Hiroshi Sugawara ,  Masami Goseki ,  Kazushi Sato

    IPC分类号： G06F1714

    CPC分类号： G06F17/147 ,  G06T9/007

    摘要： An inverse discrete-cosine transform apparatus that is simple in structure and can yet output pixel data items different in resolution. The apparatus comprises eight inverse discrete-cosine transform multipliers 23, ten field, compression, inverse discrete-cosine transform multipliers 22, eight selectors 24, eight selectors 25, eight buffers 26, eight sign multipliers 27, a control section, eight adders 28, and eight buffers 29. The control section controls the selectors 24, selectors 25, buffers 26 and sign multipliers 27 in accordance with whether the input discrete-cosine block has been subjected to field division and where the discrete-cosine coefficients are located in the block. One of the values input to the selectors 24, selectors 25, buffers 26 and sign multipliers 27 is thereby selected. The value selected is output after added with the plus sign or the minus sign. The adders 28 add the values output from the selectors 24, selectors 25, buffers 26 and sign multipliers 27. The buffers 29 store the values output from the adders 28.

    摘要翻译： 一种离散余弦变换装置，结构简单，可以输出分辨率不同的像素数据。 该装置包括八个反离散余弦变换乘法器23，十个场，压缩，反离散余弦变换乘法器22，八个选择器24，八个选择器25，八个缓冲器26，八个符号乘法器27，控制部分，八个加法器28， 和八个缓冲器29.控制部分根据输入的离散余弦块是否已经进行了场分割并且其中离散余弦系数位于块中来控制选择器24，选择器25，缓冲器26和符号乘法器27 。 由此选择输入到选择器24，选择器25，缓冲器26和符号乘法器27的值之一。 选择的值在添加加号或减号后输出。 加法器28添加从选择器24，选择器25，缓冲器26和符号乘法器27输出的值。缓冲器29存储从加法器28输出的值。

    Ring oscillator circuit for VCO
    7.
    发明授权
    Ring oscillator circuit for VCO 失效
    VCO振荡电路

    公开(公告)号：US5457429A

    公开(公告)日：1995-10-10

    申请号：US290621

    申请日：1994-08-15

    申请人： Akihide Ogawa ,  Kazuhiro Takeda ,  Masami Goseki

    发明人： Akihide Ogawa ,  Kazuhiro Takeda ,  Masami Goseki

    IPC分类号： H03K3/03 ,  H03K3/354 ,  H03L7/099

    CPC分类号： H03K3/0315 ,  H03K3/354

    摘要： In a ring oscillator type VCO in which plural stages of inverter circuits are cascade-connected to each other so as to constitute a positive feedback loop, delay amounts for both a rising edge and a falling edge of an output signal from the inverter circuit are controlled to have the same delay amount by way of a control signal. These delay amounts of the rising edge and the falling edge are controllable in such a manner that the duty ratio of an oscillator output signal is not varied. Each stage of the inverter circuit is arranged by three-stage inverters made of load transistors and driver transistors, and the control voltage is applied to the load transistors of the two adjoining inverters among the three-stage inverters.

    摘要翻译： 在多级反相器电路串联连接构成正反馈环路的环形振荡器型VCO中，控制来自逆变器电路的输出信号的上升沿和下降沿的延迟量 通过控制信号具有相同的延迟量。 上升沿和下降沿的这些延迟量可以以使得振荡器输出信号的占空比不变化的方式被控制。 逆变器电路的各级由负载晶体管和驱动晶体管构成的三级逆变器配置，并且控制电压被施加到三级逆变器中的两个相邻的反相器的负载晶体管。

    Video signal processor and TV receiver using the same
    8.
    发明授权
    Video signal processor and TV receiver using the same 失效
    视频信号处理器和电视接收机使用相同

    公开(公告)号：US07133080B2

    公开(公告)日：2006-11-07

    申请号：US10809516

    申请日：2004-03-26

    申请人： Masaya Kobayashi ,  Masami Goseki

    发明人： Masaya Kobayashi ,  Masami Goseki

    IPC分类号： H04N7/18

    CPC分类号： H04N9/78 ,  H04N5/144

    摘要： A video signal processor for improving a detection precision of Y motion and C motion, preventing erroneous judgment, and preventing deterioration of image quality without being influenced by the band of the luminance signal or the phase of a sub-carrier of chroma. The processor includes a provisional 3D Y/C separation motion detection circuit, extracting Y signals of a current frame and a past frame based on composite video signals of three adjacent lines of the current frame and the past frame, detecting Y motion in accordance with a difference of Y signals of the current frame and the past frame by a Y motion detection unit, outputting a Y motion detection signal MVDy, detecting C motion by a C motion detection unit based on Y signals of three adjacent lines in the current frame, outputting a C motion detection signal MVDc, and selecting, according to the motion detection signals MVDy and MVDc, the difference of the C signals separated from the current frame and the past frame or a predetermined value 0 to generate a C motion coefficient.

    摘要翻译： 一种视频信号处理器，用于提高Y运动和C运动的检测精度，防止错误判断，并且防止图像质量的劣化，而不受亮度信号的频带或色度子载波的相位的影响。 处理器包括临时3D Y / C分离运动检测电路，基于当前帧和过去帧的三个相邻行的合成视频信号，提取当前帧和过去帧的Y信号，根据 通过Y运动检测单元将当前帧和过去帧的Y信号的差分输出Y运动检测信号MVD ，基于三维运动检测单元的Y信号，由C运动检测单元检测C运动 当前帧中的相邻行，输出C运动检测信号MVD＆lt; C＆gt;，并且根据运动检测信号MVD＆lt; Y＆gt;和MVD＆lt; C＆lt; >，与当前帧和过去帧分离的C信号的差值或预定值0，以产生C运动系数。

    Comb filter and a video apparatus
    9.
    发明授权
    Comb filter and a video apparatus 失效
    梳状滤波器和视频设备

    公开(公告)号：US06950149B1

    公开(公告)日：2005-09-27

    申请号：US09706432

    申请日：2000-11-03

    申请人： Masami Goseki

    发明人： Masami Goseki

    IPC分类号： H04N9/78 ,  H04N9/79

    CPC分类号： H04N9/78 ,  H04N9/79

    摘要： An adaptive comb filter small in circuit scale and simple in circuit constitution is provided. The frequency band component of chrominance signal is extracted from a composite color video signal by a bandpass filter. The extracted chrominance signal is delay by a delay circuit by one horizontal period. A subtraction output is obtained by a first subtracting circuit between the output signal of the bandpass filter and the output signal of the delay circuit. An addition output is obtained by a adding circuit between the output signal of the bandpass filter and the output signal of the delay circuit. A correlation detecting circuit is provided that outputs a binary signal k0 based on a relationship between the output of the first subtracting circuit and the output of the adding circuit. This binary signal k0 and a signal k1 obtained by delaying this binary signal k0 by a second delay circuit by one horizontal period are supplied to an arithmetic block. From an operational result between the signals k0 and k1, the arithmetic block outputs a select signal for performing switching control on a selector switch circuit that switches between the output of the bandpass filter and the output of the first subtracting circuit and outputs the switched output. Then, the arithmetic block obtains the chrominance signal from the selector switch circuit.

    摘要翻译： 提供一种电路规模小，电路结构简单的自适应梳状滤波器。 通过带通滤波器从复合彩色视频信号中提取色度信号的频带分量。 提取的色度信号由延迟电路延迟一个水平周期。 通过带通滤波器的输出信号和延迟电路的输出信号之间的第一减法电路获得减法输出。 通过带通滤波器的输出信号与延迟电路的输出信号之间的相加电路获得加法输出。 提供了一种相关检测电路，其基于第一减法电路的输出和加法电路的输出之间的关系输出二进制信号k 0。 该二进制信号k 0和通过第二延迟电路将该二进制信号k 0延迟了一个水平周期而获得的信号k 1被提供给运算块。 根据信号k 0和k 1之间的运算结果，运算块输出用于对切换开关电路进行开关控制的选择信号，该选择开关电路在带通滤波器的输出和第一减法电路的输出之间切换， 输出。 然后，算术块从选择器开关电路获得色度信号。