公开(公告)号：US06735609B2

公开(公告)日：2004-05-11

申请号：US09794296

申请日：2001-02-27

申请人： Rajesh Kumar Dixit ,  Takao Terao ,  Hiroshi Sugawara ,  Masami Goseki ,  Kazushi Sato

发明人： Rajesh Kumar Dixit ,  Takao Terao ,  Hiroshi Sugawara ,  Masami Goseki ,  Kazushi Sato

IPC分类号： G06F1714

CPC分类号： G06F17/147 ,  G06T9/007

摘要： An inverse discrete-cosine transform apparatus that is simple in structure and can yet output pixel data items different in resolution. The apparatus comprises eight inverse discrete-cosine transform multipliers 23, ten field, compression, inverse discrete-cosine transform multipliers 22, eight selectors 24, eight selectors 25, eight buffers 26, eight sign multipliers 27, a control section, eight adders 28, and eight buffers 29. The control section controls the selectors 24, selectors 25, buffers 26 and sign multipliers 27 in accordance with whether the input discrete-cosine block has been subjected to field division and where the discrete-cosine coefficients are located in the block. One of the values input to the selectors 24, selectors 25, buffers 26 and sign multipliers 27 is thereby selected. The value selected is output after added with the plus sign or the minus sign. The adders 28 add the values output from the selectors 24, selectors 25, buffers 26 and sign multipliers 27. The buffers 29 store the values output from the adders 28.

摘要翻译： 一种离散余弦变换装置，结构简单，可以输出分辨率不同的像素数据。 该装置包括八个反离散余弦变换乘法器23，十个场，压缩，反离散余弦变换乘法器22，八个选择器24，八个选择器25，八个缓冲器26，八个符号乘法器27，控制部分，八个加法器28， 和八个缓冲器29.控制部分根据输入的离散余弦块是否已经进行了场分割并且其中离散余弦系数位于块中来控制选择器24，选择器25，缓冲器26和符号乘法器27 。 由此选择输入到选择器24，选择器25，缓冲器26和符号乘法器27的值之一。 选择的值在添加加号或减号后输出。 加法器28添加从选择器24，选择器25，缓冲器26和符号乘法器27输出的值。缓冲器29存储从加法器28输出的值。

公开(公告)号：US06839386B2

公开(公告)日：2005-01-04

申请号：US09734578

申请日：2000-12-13

申请人： Kazushi Sato ,  Takao Terao ,  Rajesh Kumar Dixit ,  Masami Goseki ,  Hiroshi Sugawara

发明人： Kazushi Sato ,  Takao Terao ,  Rajesh Kumar Dixit ,  Masami Goseki ,  Hiroshi Sugawara

IPC分类号： H04N1/41 ,  H04N1/17 ,  H04N11/04 ,  H04N19/105 ,  H04N19/139 ,  H04N19/176 ,  H04N19/186 ,  H04N19/33 ,  H04N19/423 ,  H04N19/44 ,  H04N19/48 ,  H04N19/50 ,  H04N19/503 ,  H04N19/51 ,  H04N19/513 ,  H04N19/587 ,  H04N19/59 ,  H04N19/60 ,  H04N19/61 ,  H04N19/625 ,  H04N19/80 ,  H04N19/85 ,  H04N7/12

CPC分类号： H04N19/59 ,  H04N19/105 ,  H04N19/112 ,  H04N19/132 ,  H04N19/137 ,  H04N19/176 ,  H04N19/18 ,  H04N19/186 ,  H04N19/80

摘要： It is targeted to prevent picture quality deterioration in the output picture information proper to the interlaced scanned picture and that ascribable to interlaced scanning. To this end, a decimating inverse discrete cosine transform unit 5 applies inverse orthogonal transform to four low-range coefficients in the horizontal direction and eight coefficients in the vertical direction among the respective coefficients of an orthogonal transform block of the compressed picture information of the input high resolution picture.

摘要翻译： 其目标是防止隔行扫描图像适当的输出图像信息的图像质量恶化，并且归因于隔行扫描。 为此，抽取逆离散余弦变换单元5对输入的压缩图像信息的正交变换块的各个系数中的水平方向的四个低范围系数和垂直方向上的八个系数应用逆正交变换 高分辨率图片。

公开(公告)号：US06549670B1

公开(公告)日：2003-04-15

申请号：US09359360

申请日：1999-07-21

申请人： Kazushi Sato ,  Kenji Komori ,  Tetsuo Kaneko ,  Satoshi Mitsuhashi ,  Masami Goseki ,  Takao Terao ,  Naofumi Yanagihara

发明人： Kazushi Sato ,  Kenji Komori ,  Tetsuo Kaneko ,  Satoshi Mitsuhashi ,  Masami Goseki ,  Takao Terao ,  Naofumi Yanagihara

IPC分类号： G06K936

CPC分类号： G06F17/147 ,  H04N19/117 ,  H04N19/122 ,  H04N19/132 ,  H04N19/154 ,  H04N19/156 ,  H04N19/159 ,  H04N19/16 ,  H04N19/176 ,  H04N19/184 ,  H04N19/186 ,  H04N19/523 ,  H04N19/59 ,  H04N19/61 ,  H04N19/80 ,  H04N19/90

摘要： An MPEG downdecoder is to be provided which eliminates pixel dephasing with the field DCT mode and the frame DCT mode without detracting from picture characteristics proper to interlaced pictures. To this end, a decimating IDCT unit 14 effectuates 4×4 decimating IDCT if the DCT mode is the field mode. If the DCT mode is a frame mode, a decimating IDCT unit 15 effectuates IDCT on the totality of coefficients of a DCT block to separate the coefficients into two pixel blocks associated with interlaced scanning. The decimating IDCT unit 15 executes DCT on the separated two pixel blocks. The low-frequency components of the two pixel blocks are processed with IDCT and the two pixel blocks are synthesized.

摘要翻译： 将提供一种使用场DCT模式和帧DCT模式消除像素去相位而不降低隔行扫描图片的图像特性的MPEG下变频器。 为此，如果DCT模式是场模式，则抽取的IDCT单元14实现4×4抽取IDCT。 如果DCT模式是帧模式，则抽取IDCT单元15对DCT块的系数的总和进行IDCT，以将系数分离成与隔行扫描相关联的两个像素块。 抽取的IDCT单元15在分离的两个像素块上执行DCT。 用IDCT处理两个像素块的低频分量，并合成两个像素块。

公开(公告)号：US06539056B1

公开(公告)日：2003-03-25

申请号：US09358451

申请日：1999-07-21

申请人： Kazushi Sato ,  Kenji Komori ,  Tetsuo Kaneko ,  Satoshi Mitsuhashi ,  Masami Goseki ,  Takao Terao ,  Naofumi Yanagihara

发明人： Kazushi Sato ,  Kenji Komori ,  Tetsuo Kaneko ,  Satoshi Mitsuhashi ,  Masami Goseki ,  Takao Terao ,  Naofumi Yanagihara

IPC分类号： H04N1102

CPC分类号： H04N19/59 ,  H04N19/117 ,  H04N19/159 ,  H04N19/16 ,  H04N19/186 ,  H04N19/48 ,  H04N19/51 ,  H04N19/523 ,  H04N19/61 ,  H04N19/90

摘要： An MPEG downdecoder is to be provided which eliminates dephasing of pixels during motion compensation to prevent deterioration of the picture quality ascribable to motion compensation. MPEG data of a high resolution picture are processed by decimating IDCT devices 14, 15 with 4×4 decimating IDCT to decode data of standard resolution picture data. In the case of the field motion prediction mode, a motion compensation device 18 interpolates respective pixels of a macro-block of reference picture data stored in a frame memory 17 to generate a macro-block constituted by pixels of ¼ pixel precision. In the case of the frame motion prediction mode, a motion compensation device 19 interpolates respective pixels of macro-block of reference picture data stored in the frame memory 17 to generate a macro-block constituted by pixels of ¼ pixel precision.

摘要翻译： 将提供一种在运动补偿期间消除像素的去相位以防止归因于运动补偿的图像质量劣化的MPEG下变频器。 通过用4×4抽取IDCT抽取IDCT设备14,15来处理高分辨率图像的MPEG数据，以对标准分辨率图像数据的数据进行解码。 在场运动预测模式的情况下，运动补偿装置18内插存储在帧存储器17中的参考图像数据的宏块的各个像素，以生成由1/4像素精度的像素构成的宏块。 在帧运动预测模式的情况下，运动补偿装置19内插存储在帧存储器17中的参考图像数据的宏块的各个像素，以生成由1/4像素精度的像素构成的宏块。

公开(公告)号：US5438303A

公开(公告)日：1995-08-01

申请号：US89566

申请日：1993-07-12

申请人： Daisuke Murakami ,  Hideki Yoshida ,  Takao Terao

发明人： Daisuke Murakami ,  Hideki Yoshida ,  Takao Terao

IPC分类号： H03K7/08

CPC分类号： H03K7/08

摘要： A pulse width modulation apparatus outputs an output pulse having an arbitrary width with respect to an arbitrary point in a pulse period. A delay means associated with a pulse cycle have multi-stage delay output means. Before a control pulse CLKP is fed to each of multi-stage delay output means, a delay time for the delay output means can be set. A rising or falling to be latched by a latch means is controlled based on delay control pulses obtained by the delay output means. An output pulse having an arbitrary pulse width with respect to an arbitrary point can be supplied without occurrence of an offset pulse or a blank duration at the start of each pulse duration.

摘要翻译： 脉冲宽度调制装置在脉冲周期内输出任意宽度相对于任意点的输出脉冲。 与脉冲周期相关联的延迟装置具有多级延迟输出装置。 在将控制脉冲CLKP馈送到多级延迟输出装置中的每一个之前，可以设置延迟输出装置的延迟时间。 基于由延迟输出装置获得的延迟控制脉冲来控制由锁存装置锁存的上升或下降。 可以提供相对于任意点具有任意脉冲宽度的输出脉冲，而不会在每个脉冲持续时间的开始处发生偏移脉冲或空白持续时间。

公开(公告)号：US06577633B1

公开(公告)日：2003-06-10

申请号：US09095624

申请日：1998-06-10

申请人： Yoshiyuki Kunito ,  Takao Terao

发明人： Yoshiyuki Kunito ,  Takao Terao

IPC分类号： H04L1228

CPC分类号： H04N21/6125 ,  H04N21/2362 ,  H04N21/2365 ,  H04N21/2381 ,  H04N21/4345 ,  H04N21/4347 ,  H04N21/4381 ,  H04N21/64307

摘要： An ATM communications device connected to an ATM network via an optical fiber improving the efficiency of the traffic in the ATM by separating the real-time data communication system and non real-time data communication system. A CPU bus (or a PCI bus) and a real-time signal bus are connected to an MPEG decoder and an MPEG encoder as real-time data processing devices. The CPU bus is connected to a CPU 18 and a memory 19 as non real-time data processing devices. The ATM communications device includes an optical link, a physical layer device, and an SAR (segmentation and reassembly) devices, carries out processing for communication of real-time data such as a video signal between the ATM network and the real-time signal bus, and carries out processing for communication of non real-time data such as computer information between the ATM network and the CPU bus.

摘要翻译： 一种通过光纤连接到ATM网络的ATM通信设备，其通过分离实时数据通信系统和非实时数据通信系统来提高ATM中业务的效率。 CPU总线（或PCI总线）和实时信号总线连接到MPEG解码器和MPEG编码器作为实时数据处理设备。 CPU总线连接到作为非实时数据处理设备的CPU 18和存储器19。 ATM通信设备包括光链路，物理层设备和SAR（分段和重组）设备，执行ATM网络与实时信号总线之间的视频信号等实时数据通信的处理 并且执行用于在ATM网络和CPU总线之间的诸如计算机信息的非实时数据的通信的处理。

公开(公告)号：US06549537B2

公开(公告)日：2003-04-15

申请号：US09076027

申请日：1998-05-11

申请人： Yoshiyuki Kunito ,  Takao Terao

发明人： Yoshiyuki Kunito ,  Takao Terao

IPC分类号： H04L1256

CPC分类号： H04Q11/0478 ,  H04L2012/5651 ,  H04L2012/5652

摘要： A communication system is disclosed which can transmit a real-time cell and a nonreal-time cell with no jitters caused in the real-time cell. When a real-time cell and nonreal-time cell are outputted at a same timing, a priority control circuit (40) passes the output timing of nonreal-time ATM cell once and sets in a flag memory (40a) a wait flag indicating that the nonreal-time cell output timing has been passed once. Also, when there is no real-time ATM cell, the priority control circuit (40) judges whether a wait flag is set in the flag memory (40a), and allows to output one nonreal-time ATM cell when a flag is set.

摘要翻译： 公开了能够在实时小区中发送不发生抖动的实时小区和非实时小区的通信系统。 当在相同定时输出实时单元和非实时单元时，优先级控制电路（40）将非实时ATM单元的输出定时一次通过，并在标志存储器（40a）中设置等待标志，该等待标志指示 非实时单元输出定时已经通过一次。 此外，当没有实时ATM信元时，优先级控制电路（40）判断在标志存储器（40a）中是否设置了等待标志，并允许在设置标志时输出一个非实时ATM信元。

公开(公告)号：US06292487B1

公开(公告)日：2001-09-18

申请号：US09076028

申请日：1998-05-11

申请人： Yoshiyuki Kunito ,  Takao Terao

发明人： Yoshiyuki Kunito ,  Takao Terao

IPC分类号： H04L1228

CPC分类号： H04Q11/0478 ,  H04L12/5601 ,  H04L2012/5652 ,  H04L2012/5664 ,  H04L2012/5674

摘要： A data transmission system is disclosed which is suitable for real-time data transmission. The data transmission system (1) comprises a data buffer (2) consisting of a real-time data buffer (3) in which real-time data is stored, and an ATM segmentation block (5) to segment a real-time data outputted from the data buffer (2) into cells each of a fixed length for transmission in an asynchronous transfer mode (ATM). The ATM segmentation block (5) consists of a real-time data transmission timing signal generating means (7) for generating transmission timing signals for the cells based on the arriving intervals of the input real-time data and a transmission VC selecting means (8) for segmenting a real-time data supplied from the date buffer 2 into cells and outputting to a physical layer device (6) the real-time data formed in the cells under the transmission timing signals generated by the cell transmission timing signal generating means (7).

摘要翻译： 公开了适用于实时数据传输的数据传输系统。数据传输系统（1）包括由实时数据存储的实时数据缓冲器（3）组成的数据缓冲器（2） 以及ATM分段块（5），其将从数据缓冲器（2）输出的实时数据分割成用于以异步传输模式（ATM）传输的固定长度的单元。 ATM分段块（5）由实时数据发送定时信号发生装置（7）组成，用于根据输入的实时数据的到达间隔和发送VC选择装置（8）生成小区的发送定时信号 ），用于将从日期缓冲器2提供的实时数据分割成单元，并将由单元发送定时信号发生装置产生的发送定时信号的单元格中形成的实时数据输出到物理层装置（6） 7）。