公开(公告)号：US07479941B2

公开(公告)日：2009-01-20

申请号：US11175137

申请日：2005-07-07

申请人： Kazuya Matsumoto ,  Yasuyuki Doi

发明人： Kazuya Matsumoto ,  Yasuyuki Doi

IPC分类号： G09G3/36

CPC分类号： G09G5/006

摘要： In order to correctly hold a low-amplitude input signal even when the operating speed of a display element drive apparatus is high, a differential signal including a pair of CLKP1 and CLKN1 is input to a first comparator and a second comparator in a manner that provides opposite phases between respective output voltage signals. An output of the first comparator is frequency-divided by the first frequency dividing flip-flop, while an output of the second comparator is frequency-divided by the second frequency dividing flip-flop. A first data holding flip-flop holds an input data signal in synchronization with a signal output by a first frequency dividing flip-flop, while a second data holding flip-flop holds an input data signal in synchronization with a signal output by a second frequency dividing flip-flop.

摘要翻译： 为了正确地保持低振幅输入信号，即使在显示元件驱动装置的操作速度高的情况下，包括一对CLKP1和CLKN1的差分信号以提供的方式输入到第一比较器和第二比较器 各个输出电压信号之间的相位相位。 第一比较器的输出被第一分频触发器分频，而第二比较器的输出被第二分频触发器分压。 第一数据保持触发器保持与由第一分频触发器输出的信号同步的输入数据信号，而第二数据保持触发器与输出的第二频率的信号同步地保持输入数据信号 分频触发器。

公开(公告)号：US20080158033A1

公开(公告)日：2008-07-03

申请号：US11965279

申请日：2007-12-27

申请人： Yasuyuki Doi ,  Makoto Hattori ,  Hisao Kunitani ,  Atsuhisa Kageyama ,  Tetsuro Oomori ,  Osamu Sarai ,  Tooru Suyama ,  Kurumi Nakayama ,  Kazuya Matsumoto

发明人： Yasuyuki Doi ,  Makoto Hattori ,  Hisao Kunitani ,  Atsuhisa Kageyama ,  Tetsuro Oomori ,  Osamu Sarai ,  Tooru Suyama ,  Kurumi Nakayama ,  Kazuya Matsumoto

IPC分类号： G09G3/36

CPC分类号： G09G3/3685 ,  G09G3/2059 ,  G09G3/3696 ,  G09G2310/027 ,  G09G2340/0428

摘要： A driving device for driving an image display system, which sequentially receives input image data corresponding to gradation of each pixel of a display image and outputs a driving voltage signal includes: an operation section for obtaining output image data of which a bit number is smaller than a bit number of the input image data based on input image data of a target pixel to be processed and input image data of a pixel in vicinity of the target pixel; a reference voltage generation section for generating a plurality of reference voltages of different levels; and a reference voltage selection section for selecting one of the plurality of reference voltages. The operation section is configured to obtain output image data of the target pixel so that a difference between the input image data and output image data of the target pixel and a difference between the input image data and output image data of the pixel in vicinity of the target pixel cancel out each other.

摘要翻译： 一种用于驱动图像显示系统的驱动装置，其顺序地接收与显示图像的每个像素的灰度对应的输入图像数据并输出驱动电压信号，包括：操作部，用于获得位数小于 基于要处理的目标像素的输入图像数据的输入图像数据的位数，并输入目标像素附近的像素的图像数据; 用于产生不同电平的多个参考电压的参考电压产生部分; 以及用于选择多个参考电压中的一个的参考电压选择部分。 操作部被配置为获得目标像素的输出图像数据，使得输入图像数据和目标像素的输出图像数据之间的差异以及输入图像数据与输入图像数据之间的像素的输出图像数据之间的差异 目标像素相互抵消。

公开(公告)号：US08432348B2

公开(公告)日：2013-04-30

申请号：US12536866

申请日：2009-08-06

申请人： Kazuya Matsumoto ,  Yasuyuki Doi

发明人： Kazuya Matsumoto ,  Yasuyuki Doi

IPC分类号： G09G3/36

CPC分类号： H03K19/018528 ,  G09G3/3688 ,  G09G2310/0294 ,  G09G2330/021

摘要： A data signal loading circuit (i) which includes: a comparator CMP1 receiving clock signal CKP and reverse-phase signal CKN of clock signal CKP, and outputting clock signal CLP1 which is in phase with clock signal CKP, and clock signal CLN 1 having a reverse phase of clock signal CKP; a comparator CMP 2 having a non-inverting input terminal receiving clock signal CLP1, and an inverting input terminal receiving clock signal CLN1; and a comparator CMP3 having an inverting input terminal receiving clock signal CLP 1, and a non-inverting input terminal receiving clock signal CLN 1, and (ii) which, by using output signals CL1 and CL2 of the comparator CMP2 and the comparator CMP3 as clock signals for latch circuits L1 and L2, equalizes delay times for the rise or fall of clock signals CL1 and CL2 inputted to the latch circuits L1 and L2, and (iii) has low power consumption.

摘要翻译： 一种数据信号加载电路（i），包括：比较器CMP1，接收时钟信号CKP的时钟信号CKP和反相信号CKN，并输出与时钟信号CKP同相的时钟信号CLP1，以及时钟信号CLN 1具有 时钟信号CKP的反向相位; 具有非反相输入端子接收时钟信号CLP1的比较器CMP2和反相输入端子接收时钟信号CLN1; 以及具有反相输入端子接收时钟信号CLP 1的比较器CMP3和非反相输入端子接收时钟信号CLN 1，以及（ii）通过使用比较器CMP2和比较器CMP3的输出信号CL1和CL2作为 用于锁存电路L1和L2的时钟信号，均衡输入到锁存电路L1和L2的时钟信号CL1和CL2的上升或下降的延迟时间，以及（iii）具有低功耗。

公开(公告)号：US20060055653A1

公开(公告)日：2006-03-16

申请号：US11175137

申请日：2005-07-07

申请人： Kazuya Matsumoto ,  Yasuyuki Doi

发明人： Kazuya Matsumoto ,  Yasuyuki Doi

IPC分类号： G09G3/36

CPC分类号： G09G5/006

摘要： In order to correctly hold a low-amplitude input signal even when the operating speed of a display element drive apparatus is high, a differential signal including a pair of CLKP1 and CLKN1 is input to a first comparator and a second comparator in a manner that provides opposite phases between respective output voltage signals. An output of the first comparator is frequency-divided by the first frequency dividing flip-flop, while an output of the second comparator is frequency-divided by the second frequency dividing flip-flop. A first data holding flip-flop holds an input data signal in synchronization with a signal output by a first frequency dividing flip-flop, while a second data holding flip-flop holds an input data signal in synchronization with a signal output by a second frequency dividing flip-flop.

公开(公告)号：US07388405B2

公开(公告)日：2008-06-17

申请号：US11513239

申请日：2006-08-31

申请人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03K19/094 ,  H03K19/0175 ,  H03B1/00

CPC分类号： H03K19/018571 ,  H03F1/0261 ,  H03F3/505 ,  H03F2200/18 ,  H04L25/028

摘要： A time required for an output voltage of a source follower to rise from Low to a predetermined voltage depends on a bias voltage. Therefore, by setting a converged voltage of an output voltage to be high by increasing the bias voltage, the time required to rise up to the predetermined voltage can be reduced. Therefore, a first source follower which is biased so that the converged value of the output voltage becomes a predetermined Hi voltage when an input data signal goes from Low to Hi, and a second source follower which is biased so as to become the Hi voltage after a period of one clock when an input data signal goes from Low to Hi, are used. The two source followers are operated with appropriate timing.

摘要翻译： 源极跟随器的输出电压从低电平上升到预定电压所需的时间取决于偏置电压。 因此，通过增加偏置电压来设定输出电压的收敛电压为高，可以降低上升到预定电压所需的时间。 因此，当输入数据信号从低电平变为高电平时，被偏压使得输出电压的会聚值变为预定的Hi电压的第一源极跟随器，以及被偏置以便成为Hi电压之后的第二源极跟随器 使用输入数据信号从低电平变为高电平时的一个时钟周期。 两个来源追随者在适当的时机运行。

公开(公告)号：US20060176091A1

公开(公告)日：2006-08-10

申请号：US11289753

申请日：2005-11-30

申请人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

发明人： Shiro Sakiyama ,  Yusuke Tokunaga ,  Shiro Dosho ,  Toru Iwata ,  Takashi Hirata ,  Hideki Yoshii ,  Yasuyuki Doi ,  Makoto Hattori

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/0891 ,  H03L7/0895

摘要： A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.

摘要翻译： 延迟元件产生延迟的时钟信号，该时钟信号以基于参考时钟信号的上升（或下降）的延迟从基于环路滤波器的输出确定的延迟量转变。 信号产生电路产生根据参考时钟信号的上升和下降以及延迟的时钟信号的转变而互补地变化的两个信号。 电荷泵电路根据这两个信号执行环路滤波器，在从参考时钟信号的上升（或下降）延迟到延迟的时钟信号的转换的延迟期间进行推（或拉） （或推动）操作在从延迟的时钟信号的转变延伸到参考时钟信号的下降（或上升）的间隔期间。

公开(公告)号：US06982706B1

公开(公告)日：2006-01-03

申请号：US10019437

申请日：2000-08-31

申请人： Yasuyuki Doi ,  Tetsuro Oomori ,  Kazuyoshi Nishi

发明人： Yasuyuki Doi ,  Tetsuro Oomori ,  Kazuyoshi Nishi

IPC分类号： G09G5/00

CPC分类号： G09G3/2011 ,  G09G3/3614 ,  G09G3/3688 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/027

摘要： A source driver 4A arranged on a liquid crystal panel includes therein in-chip reference voltage wires 17 extending from one end to the other end of an LSI chip. The source driver 4A includes therein: branch reference voltage wires 17a branching off from in-chip reference voltage wires 17; reference voltage production buffers 31; a control circuit 30 for controlling the reference voltage production buffers 31; a reference voltage production resistor section 32 for subdividing the reference voltage into values of n steps; voltage level selection circuits 34 each for selecting one of the subdivided voltages; and output buffers 35. Since the reference voltages are supplied to each source driver 4 via wiring for connecting the in-chip reference voltage wires 17 in series with one another, the wiring structure for supplying the reference voltages can be simplified.

摘要翻译： 布置在液晶面板上的源极驱动器4A包括从LSI芯片的一端延伸到另一端的片上参考电压电线17。 源极驱动器4A包括：从芯片上参考电压线17分支的分支参考电压线17a; 参考电压产生缓冲器31; 用于控制参考电压产生缓冲器31的控制电路30; 参考电压产生电阻器部分32，用于将参考电压分为n个步骤的值; 每个电压电平选择电路34用于选择一个分割电压; 和输出缓冲器35。 由于通过用于将片上参考电压线17串联连接的布线将参考电压提供给每个源极驱动器4，因此可以简化用于提供参考电压的布线结构。

公开(公告)号：US06392485B1

公开(公告)日：2002-05-21

申请号：US09663388

申请日：2000-09-15

申请人： Yasuyuki Doi ,  Tetsuro Oomori

发明人： Yasuyuki Doi ,  Tetsuro Oomori

IPC分类号： H03F345

CPC分类号： H03F3/45219 ,  G09G3/3688 ,  H03F3/4565 ,  H03F3/68 ,  H03F2203/45431 ,  H03F2203/45448 ,  H03F2203/45451

摘要： It is an object of the present invention to provide a high slew rate differential amplifier circuit that can reduce current consumption while maintaining stability. A P-type MOS sub-current source (6) having a current source circuit including a transistor (M18) having a gate voltage of a P-type MOS output transistor (M15) input to a gate thereof and a constant current source transistor (M17) connected in series with the transistor (M18), the current source circuit being connected in parallel with a constant current source transistor (M1) of a P-type MOS differential input section (1) is combined with an N-type MOS sub-current source (7) including a current source circuit including a transistor (M19) having a gate voltage of an N-type MOS output transistor (M16) input to a gate thereof and a constant current source transistor (M20) connected in series with the transistor (M19), the current source circuit being connected in parallel with a constant current source transistor (M6) of an N-type MOS differential input section (2). To increase a current through the differential input section when a high slew rate is required, the current source circuit including the transistor having the gate voltage of the output transistor input to the gate thereof and the constant current source transistor connected in series with the first transistor is used as a sub-current source for a differential circuit, in order to reduce a steady-state current.

摘要翻译： 本发明的目的是提供一种可以在保持稳定性的同时降低电流消耗的高压摆率差分放大器电路。 一种具有电流源电路的P型MOS子电流源（6），包括具有输入到其栅极的P型MOS输出晶体管（M15）的栅极电压的晶体管（M18）和恒流源晶体管 M17），与P型MOS差分输入部（1）的恒流源晶体管（M1）并联连接的电流源电路与N型MOS子晶体管（M18）组合， 电流源（7），包括电流源电路，其包括具有输入到其栅极的N型MOS输出晶体管（M16）的栅极电压的晶体管（M19）和与栅极串联连接的恒流源晶体管（M20） 所述晶体管（M19），所述电流源电路与N型MOS差分输入部（2）的恒流源晶体管（M6）并联连接。 为了在需要高压摆率时增加通过差分输入部分的电流，电流源电路包括输入到其栅极的输出晶体管的栅极电压的晶体管和与第一晶体管串联连接的恒流源晶体管 被用作差分电路的子电流源，以便降低稳态电流。

公开(公告)号：US20110199400A1

公开(公告)日：2011-08-18

申请号：US13093524

申请日：2011-04-25

申请人： Hideki Ikeda ,  Yasuyuki Doi

发明人： Hideki Ikeda ,  Yasuyuki Doi

IPC分类号： G09G5/10

CPC分类号： G09G3/3614 ,  G02F2203/30 ,  G09G3/3685 ,  G09G3/3696

摘要： Gradation wiring lines of positive polarity included in a (m)th group of wiring lines of positive polarity and gradation wiring lines of positive polarity included in a (m+1)th group of wiring lines of positive polarity are alternately provided. Gradation wiring lines of negative polarity included in a (m′)th group of wiring lines of negative polarity and gradation wiring lines of negative polarity included in a (m′+1)th group of wiring lines of negative polarity are alternately provided. First −(n) th resistance dividing circuits of positive polarity include (m)th resistance dividing circuits of positive polarity provided between the gradation wiring lines of positive polarity or on one end side of a direction where the gradation wiring lines of positive polarity extend and connected to the (m)th group of wiring lines of positive polarity, and (m+1)th resistance dividing circuits of positive polarity provided between the gradation wiring lines of positive polarity or on the other end side of the direction where the gradation wiring lines of positive polarity extend and connected to the (m+1)th group of wiring lines of positive polarity. First −(n′)th resistance dividing circuits of negative polarity include (m′)th resistance dividing circuits of negative polarity provided between the gradation wiring lines of negative polarity or on one end side of a direction where the gradation wiring lines of negative polarity extend and connected to the (m′)th group of wiring lines of negative polarity, and (m′+1)th resistance dividing circuits of negative polarity provided between the gradation wiring lines of negative polarity or on the other end side of the direction where the gradation wiring lines of negative polarity extend and connected to the (m′+1)th group of wiring lines of negative polarity.

公开(公告)号：US20100225518A1

公开(公告)日：2010-09-09

申请号：US12376400

申请日：2007-06-19

申请人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Kurumi Nakayama

发明人： Yusuke Tokunaga ,  Shiro Sakiyama ,  Shiro Dosho ,  Yasuyuki Doi ,  Kurumi Nakayama

IPC分类号： H03M1/66

CPC分类号： G09G3/3685 ,  G09G3/3696 ,  G09G2310/027 ,  H03M1/76

摘要： A selection section (105) selects a step voltage, among a plurality of step voltages (SV1, SV2, SV3, . . . ) each having a voltage value changing stepwise, corresponding to the digital value of digital data (D-DATA). For each of the plurality of step voltages (SV1, SV2, SV3, . . . ), different digital values are allocated to different steps of the step voltage. An amplifier section (106) amplifies the step voltage selected by the selection section (105). An output section (107) outputs the step voltage amplified by the amplifier section (106) as an output voltage (Vout) for a time period corresponding to the digital value of the digital data (D-DATA).

摘要翻译： 选择部（105）选择与数字数据（D-DATA）的数字值对应的，具有逐步变化的电压值的多个阶梯电压（SV1，SV2，SV3 ......等）中的阶梯电压。 对于多个步进电压（SV1，SV2，SV3 ...）中的每一个，将不同的数字值分配给步进电压的不同步骤。 放大器部分（106）放大由选择部分（105）选择的步进电压。 输出部分（107）输出由放大器部分（106）放大的阶跃电压作为对应于数字数据（D-DATA）的数字值的时间周期的输出电压（Vout）。