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    Stacked semiconductor device
    1.
    发明授权
    Stacked semiconductor device 失效
    堆叠半导体器件

    公开(公告)号：US5128732A

    公开(公告)日：1992-07-07

    申请号：US199439

    申请日：1988-05-27

    申请人： Kazuyuki Sugahara ,  Tadashi Nishimura ,  Shigeru Kusunoki ,  Yasuo Inoue ,  Yasuo Yamaguchi

    发明人： Kazuyuki Sugahara ,  Tadashi Nishimura ,  Shigeru Kusunoki ,  Yasuo Inoue ,  Yasuo Yamaguchi

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0688

    摘要： A stacked semiconductor device has three-dimensional alternate layers of iconductor elements and insulating layers each electrically insulating the adjacent upper and lower layers of semiconductor elements, formed on a single crystal semiconductor substrate. A semiconductor is deposited in openings formed respectively in the insulating layers to form single crystal semiconductor layers each having the same crystal axis as the single crystal semiconductor substrate respectively over the insulating layers, and semiconductor elements are formed respectively in a plurality of layers. The opening formed through the upper insulating layer reaches the lower layer of the semiconductor element immediately below the same upper insulating layer, and is formed at a position spaced apart horizontally from the opening formed through the lower insulating layer immediately below the same upper insulating layer. A semiconductor for forming the upper layer of a semiconductor having the same crystal axis as the lower layer of a semiconductor is deposited in the opening of the upper insulating layer so that satisfactory lateral epitaxial growth will occur over the insulating layer.

    摘要翻译： 叠层半导体器件具有三维交替层的半导体元件和绝缘层，每个绝缘层将形成在单晶半导体衬底上的相邻的半导体元件的上层和下层电绝缘。 分别在绝缘层中形成的开口中沉积半导体，以形成分别在绝缘层上分别与单晶半导体衬底相同的晶轴的单晶半导体层，并分别形成多个半导体元件。 通过上绝缘层形成的开口到达同一上绝缘层正下方的半导体元件的下层，并形成在与通过同一上绝缘层正下方的下绝缘层形成的开口水平间隔开的位置处。 用于形成具有与半导体的下层相同的晶轴的半导体的上层的半导体被沉积在上绝缘层的开口中，使得在绝缘层上将发生令人满意的横向外延生长。

    Semiconductor device and manufacturing method thereof
    2.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US5413968A

    公开(公告)日：1995-05-09

    申请号：US22876

    申请日：1993-02-25

    申请人： Yasuo Inoue ,  Kazuyuki Sugahara ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Tadashi Nishimura

    发明人： Yasuo Inoue ,  Kazuyuki Sugahara ,  Takashi Ipposhi ,  Yasuo Yamaguchi ,  Tadashi Nishimura

    IPC分类号： H01L21/3205 ,  H01L21/285 ,  H01L21/768 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L27/11 ,  H01L21/44

    CPC分类号： H01L21/28518 ,  H01L23/485 ,  H01L27/11 ,  H01L27/1112 ,  H01L2924/0002

    摘要： A semiconductor device includes a conductor layer (3, 7) having a silicon crystal, an insulator layer (5, 15) formed on the surface of the conductor layer (3, 7) having a contact hole therethrough to said surface of the conductor layer (3, 7), an interconnecting portion formed at a predetermined location in the insulator layer (5, 15) and having a contact hole (6, 9) the bottom surface of which becomes the surface of the conductor layer (3, 7), a barrier layer (14) formed at the bottom of said contact hole at least on the surface of the conductor layer (3, 7) in the interconnecting portion, and a metal silicide layer (12) formed on the barrier layer (14). This semiconductor device is manufactured by depositing the insulator layer (5, 15) having the contact hole (6, 9) on the conductor layer (3, 7) having the silicon crystal, forming the barrier layer (14) and the polysilicon layer (7, 10) overlapping each other in the contact hole (6, 9) and on the insulator layer (5, 15) and then patterning these overlapping barrier layer (14) and polysilicon layer (7, 10), forming a metal layer (8, 11) thereon to be silicidized, and removing unreacted metal. The semiconductor device thus manufactured prevents a suction of silicon from the conductor layer (3, 7) to the metal silicide layer (12) and hence prevents an increase in resistance value due to a deficiency of silicon produced in the conductor layer (3, 7), thereby minimizing a series resistance of the metal silicide layer (12), a contact portion and the conductor layer (3, 7).

    摘要翻译： 半导体器件包括具有硅晶体的导体层（3,7），形成在导体层（3,7）的表面上的绝缘体层（5,15），其具有穿过其的导体层的所述表面的接触孔 （3,7），形成在所述绝缘体层（5,15）中的预定位置处并具有其底表面成为所述导体层（3,7）的表面的接触孔（6,9）的互连部分， 至少在所述互连部分中的所述导体层（3,7）的表面上形成在所述接触孔的底部处的阻挡层（14）和形成在所述阻挡层（14）上的金属硅化物层（12） 。 该半导体器件通过在具有硅晶体的导体层（3,7）上沉积具有接触孔（6,9）的绝缘体层（5,15），形成阻挡层（14）和多晶硅层（ 7,10）在接触孔（6,9）和绝缘体层（5,15）上彼此重叠，然后对这些重叠的阻挡层（14）和多晶硅层（7,10）进行构图，形成金属层 8,11）在其上被硅化，并除去未反应的金属。 这样制造的半导体器件防止硅从导体层（3,7）吸收到金属硅化物层（12），从而防止由于导体层（3,7）中产生的硅的缺陷导致的电阻值增加 ），从而使金属硅化物层（12），接触部分和导体层（3,7）的串联电阻最小化。

    Semiconductor device and method of manufacturing the same
    3.
    发明授权
    Semiconductor device and method of manufacturing the same 失效
    半导体装置及其制造方法

    公开(公告)号：US06727552B2

    公开(公告)日：2004-04-27

    申请号：US10062462

    申请日：2002-02-05

    申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    IPC分类号： H01L2701

    CPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L23/4825 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

    摘要翻译： 根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。 结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。 因此，可以完全防止闭锁。 结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地 设置妨碍高集成度的身体接触区域及其制造方法。

    Semiconductor device having a common substrate bias
    6.
    发明授权
    Semiconductor device having a common substrate bias 失效
    具有公共衬底偏置的半导体器件

    公开(公告)号：US06198134B1

    公开(公告)日：2001-03-06

    申请号：US09056616

    申请日：1998-04-08

    申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    IPC分类号： H01L2701

    CPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L23/4825 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

    摘要翻译： 根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。 结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。 因此，可以完全防止闭锁。 结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地 设置妨碍高集成度的身体接触区域及其制造方法。

    Semiconductor device having different field oxide sizes
    9.
    发明授权
    Semiconductor device having different field oxide sizes 有权
    具有不同场氧化物尺寸的半导体器件

    公开(公告)号：US06351014B2

    公开(公告)日：2002-02-26

    申请号：US09519598

    申请日：2000-03-06

    申请人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    发明人： Yasuo Inoue ,  Tadashi Nishimura ,  Yasuo Yamaguchi ,  Toshiaki Iwamatsu

    IPC分类号： H01L2701

    CPC分类号： H01L21/8238 ,  H01L21/84 ,  H01L23/4825 ,  H01L27/0921 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78615 ,  H01L29/78621 ,  H01L29/78645 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

    摘要： According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

    摘要翻译： 根据本发明的半导体器件，形成场致氧化膜以覆盖SOI层的主表面并到达掩埋氧化膜的主表面。 结果，可以完全电隔离SOI的pMOS有源区和SOI的nMOS有源区。 因此，可以完全防止闭锁。 结果，可以提供使用SOI衬底的半导体器件，该SOI衬底可以通过消除源极和漏极之间的击穿电压的降低来实现高集成度，这是常规SOI场效应晶体管的问题，以及有效地 设置妨碍高集成度的身体接触区域及其制造方法。