公开(公告)号：US20110254827A1

公开(公告)日：2011-10-20

申请号：US13088482

申请日：2011-04-18

申请人： Kei TAMURA ,  Takumi Shigaki ,  Hideo Sato ,  Shouji Nagao ,  Mitsuru Goto

发明人： Kei TAMURA ,  Takumi Shigaki ,  Hideo Sato ,  Shouji Nagao ,  Mitsuru Goto

IPC分类号： G06F3/038

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G2300/0426 ,  G09G2300/0434 ,  G09G2310/0251 ,  G09G2310/067 ,  G09G2320/0209

摘要： Provided are a display device and a method of driving the same, improving display quality by suppressing abnormal changes resulting from parasitic capacitance. The display device includes first and second pixel circuits having first and second switching elements and first and second display electrodes; and a display control voltage supply unit supplying a display control voltage to the first and second display electrodes. In a first write period, the display control voltage supply unit turns ON the first and second switching elements and supplies a display control voltage corresponding to display data of the first pixel circuit to the first and second display electrodes. In a second write period, the display control voltage supply unit maintains the switch of the second switching element to be in the ON state and supplies a display control voltage corresponding to display data of the second pixel circuit to the second display electrode.

摘要翻译： 提供一种显示装置及其驱动方法，通过抑制由寄生电容引起的异常变化来提高显示质量。 显示装置包括具有第一和第二开关元件的第一和第二像素电路以及第一和第二显示电极; 以及向第一和第二显示电极提供显示控制电压的显示控制电压供应单元。 在第一写入周期中，显示控制电压提供单元接通第一和第二开关元件，并将与第一像素电路的显示数据相对应的显示控制电压提供给第一和第二显示电极。 在第二写入周期中，显示控制电压提供单元将第二开关元件的开关保持为导通状态，并将与第二像素电路的显示数据相对应的显示控制电压提供给第二显示电极。

公开(公告)号：US08217885B2

公开(公告)日：2012-07-10

申请号：US12379521

申请日：2009-02-24

申请人： Toshio Miyazawa ,  Masahiro Maki ,  Hideo Sato ,  Takumi Shigaki

发明人： Toshio Miyazawa ,  Masahiro Maki ,  Hideo Sato ,  Takumi Shigaki

IPC分类号： G09G3/36 ,  G11C19/00

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2310/0286 ,  G11C19/184

摘要： In a display device which includes a driver circuit having a shift register circuit, the shift register circuit is constituted of basic circuits in plural stages. Each basic circuit is constituted of a circuit A, a circuit B and a circuit C. The circuit A fetches a first drive clock (or a second drive clock) inputted from the outside when transfer data is inputted to the circuit A from a circuit of preceding stage, outputs the transfer data as a shift output of own stage, and transfers the transfer data to the circuit B. The circuit B transfers the transfer data to the circuit A of the basic circuit of the succeeding stage, and resets the circuit C. The circuit C resets the circuit A and the circuit B in synchronism with the first drive clock (or the second drive clock) generated at next timing or succeeding timing of the first drive clock.

摘要翻译： 在包括具有移位寄存器电路的驱动电路的显示装置中，移位寄存器电路由多级的基本电路构成。 每个基本电路由电路A，电路B和电路C构成。当传输数据从电路A的电路输入到电路A时，电路A取出从外部输入的第一驱动时钟（或第二驱动时钟） 输出传输数据作为自身级的移位输出，并将传送数据传送到电路B.电路B将传送数据传送到后级基本电路的电路A，并将电路C 电路C与在第一驱动时钟的下一定时或后续定时产生的第一驱动时钟（或第二驱动时钟）同步地复位电路A和电路B.

公开(公告)号：US20090225063A1

公开(公告)日：2009-09-10

申请号：US12398326

申请日：2009-03-05

申请人： Takumi Shigaki ,  Toshio Miyazawa ,  Hideo Sato ,  Masahiro Maki

发明人： Takumi Shigaki ,  Toshio Miyazawa ,  Hideo Sato ,  Masahiro Maki

IPC分类号： G09G5/00

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3655 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/06 ,  G11C19/28 ,  G11C19/287

摘要： A display device which enhances time-wise likelihood for a leak current from a floating memory node by increasing the number of writing of a voltage to a floating memory node is provided. In the display device, a vertical driver circuit includes a shift register circuit and a common electrode driver circuit. The shift register circuit is constituted of a plurality of basic circuits which outputs common electrode driving pulses based on a transfer clock inputted from the outside. The common electrode driver circuit is constituted of a plurality of common basic circuits to which the respective common electrode driving pulses outputted from the respective basic circuits of the shift register circuit and the transfer clock are inputted. Each common basic circuit includes: a circuit A which fetches an AC signal based on the common electrode driving pulse; a circuit B which outputs, based on the AC signal fetched by the circuit A, a first common voltage or a second common voltage which differs from the first common voltage in voltage level to the common electrodes corresponding to the AC signal; and a circuit C which holds a state of the circuit B based on the transfer clock.

摘要翻译： 提供一种显示装置，其通过增加向浮动存储器节点写入电压的数量来增强来自浮动存储器节点的泄漏电流的时间上的可能性。 在显示装置中，垂直驱动电路包括移位寄存器电路和公共电极驱动电路。 移位寄存器电路由基于从外部输入的传送时钟输出公共电极驱动脉冲的多个基本电路构成。 公共电极驱动电路由输入从移位寄存器电路和传送时钟的各基本电路输出的各公共电极驱动脉冲的多个公共基本电路构成。 每个公共基本电路包括：基于公共电极驱动脉冲取出AC信号的电路A; 基于由电路A取得的交流信号输出与电压电平上的第一公共电压不同于对应于交流信号的公共电极的第一公共电压或第二公共电压的电路B; 以及基于传送时钟保持电路B的状态的电路C.

公开(公告)号：US08508513B2

公开(公告)日：2013-08-13

申请号：US12398326

申请日：2009-03-05

申请人： Takumi Shigaki ,  Toshio Miyazawa ,  Hideo Sato ,  Masahiro Maki

发明人： Takumi Shigaki ,  Toshio Miyazawa ,  Hideo Sato ,  Masahiro Maki

IPC分类号： G09G5/00

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3655 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/06 ,  G11C19/28 ,  G11C19/287

摘要： A display device which enhances time-wise likelihood for a leak current from a floating memory node by increasing the number of writings of a voltage to a floating memory node. A vertical driver includes: a shift register including basic circuits which output common electrode driving pulses based on a transfer; and a common electrode driver including common basic circuits which receive the common electrode driving pulses and the transfer clock. Each common basic circuit includes: a circuit A which fetches an AC signal based on the common electrode driving pulse; a circuit B which outputs, based on the AC signal, a first common voltage or a second common voltage which differs from the first common voltage in voltage level to the common electrodes corresponding to the AC signal; and a circuit C which holds a state of the circuit B based on the transfer clock.

摘要翻译： 一种显示装置，其通过将电压写入数量增加到浮动存储器节点来增强来自浮动存储器节点的泄漏电流的时间似然。 垂直驱动器包括：移位寄存器，包括基于转移输出公共电极驱动脉冲的基本电路; 以及公共电极驱动器，其包括接收公共电极驱动脉冲和传送时钟的公共基本电路。 每个公共基本电路包括：基于公共电极驱动脉冲取出AC信号的电路A; 电路B，其基于所述AC信号，将与所述AC信号对应的公共电极的电压电平的第一公共电压不同的第一公共电压或第二公共电压输出; 以及基于传送时钟保持电路B的状态的电路C.

公开(公告)号：US08872749B2

公开(公告)日：2014-10-28

申请号：US12155981

申请日：2008-06-12

申请人： Takumi Shigaki ,  Hideo Sato ,  Masahiro Maki

发明人： Takumi Shigaki ,  Hideo Sato ,  Masahiro Maki

IPC分类号： G09G3/36 ,  G11C19/18

CPC分类号： G11C19/184 ,  G09G3/3674 ,  G09G2310/0286

摘要： A shift register circuit has a plurality of shift pulse generation circuits, and a scanning voltage generation circuit has a plurality of base circuits. The base circuits are presented with a first shift pulse generated by a shift pulse generation circuit, and a scanning line clock. The base circuits have a first transistor in which the first shift pulse is input to a first electrode, and a first power supply voltage is input to a control electrode; and a second transistor in which a control electrode is connected to a second electrode in the first transistor, a scanning line clock is input to the first electrode, and the second electrode is connected to a scanning voltage output terminal. The base circuits output a selected scanning voltage synchronized with the scanning line clock from the scanning voltage output terminal when the first shift pulse is at a first voltage level.

摘要翻译： 移位寄存器电路具有多个移位脉冲发生电路，扫描电压产生电路具有多个基极电路。 基本电路呈现由移位脉冲发生电路和扫描线时钟产生的第一移位脉冲。 基极具有第一晶体管，其中第一移位脉冲被输入到第一电极，第一电源电压被输入到控制电极; 以及第二晶体管，其中控制电极连接到所述第一晶体管中的第二电极，扫描线时钟被输入到所述第一电极，并且所述第二电极连接到扫描电压输出端子。 当第一移位脉冲处于第一电压电平时，基极电路从扫描电压输出端子输出与扫描线时钟同步的所选扫描电压。

公开(公告)号：US20090225019A1

公开(公告)日：2009-09-10

申请号：US12379521

申请日：2009-02-24

申请人： Toshio Miyazawa ,  Masahiro Maki ,  Hideo Sato ,  Takumi Shigaki

发明人： Toshio Miyazawa ,  Masahiro Maki ,  Hideo Sato ,  Takumi Shigaki

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G3/3688 ,  G09G2310/0286 ,  G11C19/184

摘要： In a display device which includes a driver circuit having a shift register circuit, the shift register circuit is constituted of basic circuits in plural stages. Each basic circuit is constituted of a circuit A, a circuit B and a circuit C. The circuit A fetches a first drive clock (or a second drive clock) inputted from the outside when transfer data is inputted to the circuit A from a circuit of preceding stage, outputs the transfer data as a shift output of own stage, and transfers the transfer data to the circuit B. The circuit B transfers the transfer data to the circuit A of the basic circuit of the succeeding stage, and resets the circuit C. The circuit C resets the circuit A and the circuit B in synchronism with the first drive clock (or the second drive clock) generated at next timing or succeeding timing of the first drive clock.

摘要翻译： 在包括具有移位寄存器电路的驱动电路的显示装置中，移位寄存器电路由多级的基本电路构成。 每个基本电路由电路A，电路B和电路C构成。当传输数据从电路A的电路输入到电路A时，电路A取出从外部输入的第一驱动时钟（或第二驱动时钟） 输出传输数据作为自身级的移位输出，并将传送数据传送到电路B.电路B将传送数据传送到后级基本电路的电路A，并将电路C 电路C与在第一驱动时钟的下一定时或后续定时产生的第一驱动时钟（或第二驱动时钟）同步地复位电路A和电路B.

公开(公告)号：US20080316156A1

公开(公告)日：2008-12-25

申请号：US12155981

申请日：2008-06-12

申请人： Takumi Shigaki ,  Hideo Sato ,  Masahiro Maki

发明人： Takumi Shigaki ,  Hideo Sato ,  Masahiro Maki

IPC分类号： G09G3/36

CPC分类号： G11C19/184 ,  G09G3/3674 ,  G09G2310/0286

摘要： A shift register circuit has a plurality of shift pulse generation circuits, and a scanning voltage generation circuit has a plurality of base circuits. The base circuits are presented with a first shift pulse generated by a shift pulse generation circuit, and a scanning line clock. The base circuits have a first transistor in which the first shift pulse is input to a first electrode, and a first power supply voltage is input to a control electrode; and a second transistor in which a control electrode is connected to a second electrode in the first transistor, a scanning line clock is input to the first electrode, and the second electrode is connected to a scanning voltage output terminal. The base circuits output a selected scanning voltage synchronized with the scanning line clock from the scanning voltage output terminal when the first shift pulse is at a first voltage level.

摘要翻译： 移位寄存器电路具有多个移位脉冲发生电路，扫描电压产生电路具有多个基极电路。 基本电路呈现由移位脉冲发生电路和扫描线时钟产生的第一移位脉冲。 基极具有第一晶体管，其中第一移位脉冲被输入到第一电极，第一电源电压被输入到控制电极; 以及第二晶体管，其中控制电极连接到所述第一晶体管中的第二电极，扫描线时钟被输入到所述第一电极，并且所述第二电极连接到扫描电压输出端子。 当第一移位脉冲处于第一电压电平时，基极电路从扫描电压输出端子输出与扫描线时钟同步的所选扫描电压。

公开(公告)号：US20100032674A1

公开(公告)日：2010-02-11

申请号：US12536097

申请日：2009-08-05

申请人： Takeshi Noda ,  Toshio Miyazawa ,  Takuo Kaitoh ,  Takumi Shigaki

发明人： Takeshi Noda ,  Toshio Miyazawa ,  Takuo Kaitoh ,  Takumi Shigaki

IPC分类号： H01L33/00

CPC分类号： G02F1/13624 ,  G02F2202/104

摘要： An object of the present invention is to provide a display device where small thin film transistors with a lower off current can be formed. The present invention provides a display device where thin film transistors are formed on a substrate, and in the above described thin film transistors, a gate electrode is formed on a semiconductor layer with a gate insulating film in between, the above described thin film transistors are formed of at least a first thin film transistor and a second thin film transistor, and the above described semiconductor layer is divided into individual regions for each film transistor, the above described semiconductor layer is provided with a common region shared either by the drain region of the above described first thin film transistor and the source region of the above described second thin film transistor or by the source region of the above described first thin film transistor and the drain region of the above described second thin film transistor, in the first thin film transistor and the second thin film transistor, the semiconductor layer is provided with LDD regions where the impurity concentration is lower than in the above described drain region and the above described source region, between the channel region and the drain region, as well as between the channel region and the source region, and the above described gate electrode is formed so as to overlap with the above described common region in the above described semiconductor layer and face at least the above described channel region and the above described LDD regions of the above described first thin film transistor and the above described channel region and the above described LDD regions of the above described second thin film transistor.

摘要翻译： 本发明的目的是提供一种可以形成具有较低截止电流的小型薄膜晶体管的显示装置。 本发明提供了一种在基板上形成薄膜晶体管的显示装置，在上述薄膜晶体管中，在半导体层之间形成有栅极绝缘膜的栅电极，上述薄膜晶体管 由至少第一薄膜晶体管和第二薄膜晶体管形成，并且上述半导体层被分成用于每个薄膜晶体管的各个区域，上述半导体层设置有共同区域，其共同区域由 上述第一薄膜晶体管和上述第二薄膜晶体管的源极区域或上述第一薄膜晶体管的源极区域和上述第二薄膜晶体管的漏极区域在第一薄膜 晶体管和第二薄膜晶体管，半导体层设置有LDD区，其中杂质c 浓度低于上述漏极区域和上述源极区域，沟道区域和漏极区域之间以及沟道区域和源极区域之间，并且上述栅极电极形成为重叠 在上述半导体层中具有上述公共区域并且至少面向上述第一薄膜晶体管的上述沟道区域和上述LDD区域以及上述沟道区域和上述上述LDD区域 描述的第二薄膜晶体管。

公开(公告)号：US08124974B2

公开(公告)日：2012-02-28

申请号：US12536097

申请日：2009-08-05

申请人： Takeshi Noda ,  Toshio Miyazawa ,  Takuo Kaitoh ,  Takumi Shigaki

发明人： Takeshi Noda ,  Toshio Miyazawa ,  Takuo Kaitoh ,  Takumi Shigaki

IPC分类号： H01L33/00

CPC分类号： G02F1/13624 ,  G02F2202/104

摘要： A display device is provided in which at least first and second thin film transistors are formed on a substrate, including a gate electrode formed on a semiconductor layer with a gate insulating film in between. The semiconductor layer is divided into individual regions for each film transistor, and is provided with a common region and LDD regions between a channel region and a drain region, as well as between the channel region and a source region. The gate electrode is formed as an integrated gate electrode for the first and second thin film transistors that faces the common region, the channel region and the LDD regions of the first thin film transistor and the channel region and the LDD regions of the second thin film transistor.

摘要翻译： 提供了一种显示装置，其中至少第一和第二薄膜晶体管形成在基板上，包括形成在其间具有栅极绝缘膜的半导体层上的栅电极。 半导体层被分成用于每个薄膜晶体管的单个区域，并且在沟道区域和漏极区域之间以及在沟道区域和源极区域之间设置有公共区域和LDD区域。 栅电极形成为第一和第二薄膜晶体管的集成栅电极，其面对公共区域，第一薄膜晶体管的沟道区域和LDD区域以及第二薄膜的沟道区域和LDD区域 晶体管。