公开(公告)号：US6147890A

公开(公告)日：2000-11-14

申请号：US166503

申请日：1998-10-05

申请人： Keiichi Kawana ,  Michael D. Rostoker

发明人： Keiichi Kawana ,  Michael D. Rostoker

IPC分类号： G11C15/00 ,  H03K19/177

CPC分类号： H03K19/1776 ,  G11C15/00

摘要： Content Addressable Memory (CAM) core is integrated and interfaced with a configurable logic core (e.g., FPGA) on a single integrated circuit (IC) chip to permit a user to change algorithms for and to tailor word length to a particular application. Significant improvements in fetch times and overhead are achieved. An electronic component (e.g., integrated circuit) incorporating the technique is suitably included in a system or subsystem having electrical functionality, such as general purpose computers, telecommunications devices, and the like.

摘要翻译： 内容可寻址存储器（CAM）核心集成在单个集成电路（IC）芯片上与可配置的逻辑核心（例如FPGA）接口，以允许用户改变用于特定应用的字长的算法和定制字长度。 实现了提取时间和开销的显着改进。 结合该技术的电子部件（例如，集成电路）适当地包括在具有电功能的系统或子系统中，例如通用计算机，电信设备等。

公开(公告)号：US5282164A

公开(公告)日：1994-01-25

申请号：US796686

申请日：1991-11-25

申请人： Keiichi Kawana

发明人： Keiichi Kawana

IPC分类号： H03K19/173 ,  H03K19/177 ,  G11C7/00 ,  G06F7/38 ,  G11C19/00

CPC分类号： H03K19/177 ,  H03K19/17704

摘要： A programmable integrated circuit of the present invention can change the input system of serial/parallel input-parallel output circuit for program data from serial to parallel or vice versa in response to a control signal from control signal input. Therefore, a program can be written at a relatively low speed through the parallel output of serial input, and a program can be written at a relatively high speed by inputting data in parallel and outputting the input data in parallel. Moreover, the bit width of the aforementioned serial/parallel input-parallel output circuit can be changed in response to a control signal from control signal input, whereby bit width for data input, shift and the like can be optimized according to the quantity of programs to be written with the result of improved freedom of users and the reduced time required for writing a large quantity of programs.

摘要翻译： 本发明的可编程集成电路可以响应于来自控制信号输入的控制信号，将串行/并行输入并行输出电路的输入系统从串行转换为并行或反之亦然。 因此，可以通过串行输入的并行输出以相对低的速度写入程序，并且通过并行输入数据并且并行地输出输入数据，可以以较高的速度写入程序。 此外，可以响应于来自控制信号输入的控制信号来改变上述串行/并行输入并行输出电路的位宽，从而可以根据程序的数量来优化用于数据输入，移位等的位宽度 由于改善了用户自由，减少了编写大量程序所需的时间。

公开(公告)号：US5327023A

公开(公告)日：1994-07-05

申请号：US857986

申请日：1992-03-26

申请人： Keiichi Kawana ,  Norimitsu Sako

发明人： Keiichi Kawana ,  Norimitsu Sako

IPC分类号： H03K19/177 ,  H03K19/173

CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17792

摘要： A programmable logic device of the present invention is constructed to reduce the number of switching elements in wire switches when programmably connecting logical elements by using wire groups. A plurality of programmable wire groups are wired in vertical and horizontal channels between logical elements arranged in array. The wire groups are combined to intersect preferably in crosses. The wire groups are short-circuit-connected at the intersections or connected through programmable switching elements. Programmable connections are effected through wire switching means middled between the wire elements provided between the adjacent intersections. Hence, the programmable logic device of this invention is capable of reducing the areas occupied by the switching elements in the switching means and attaining a high degree of freedom of wiring and a high integration.

摘要翻译： 本发明的可编程逻辑器件被构造为在可编程地通过使用线组连接逻辑元件时减少有线开关中的开关元件的数量。 多个可编程线组在布置成阵列的逻辑元件之间的垂直和水平通道中布线。 电线组合在一起，最好在十字架上相交。 导线组在交叉点处短路连接或通过可编程开关元件连接。 可编程连接通过设置在相邻交叉点之间的线元件之间的线切换装置来实现。 因此，本发明的可编程逻辑器件能够减少开关元件中的开关元件占用的面积，并且能够实现高度的布线自由度和高集成度。

公开(公告)号：US5338982A

公开(公告)日：1994-08-16

申请号：US857974

申请日：1992-03-26

申请人： Keiichi Kawana

发明人： Keiichi Kawana

IPC分类号： H03K19/173

CPC分类号： H03K19/1736

摘要： A semiconductor integrated circuit capable of electrically writing functions according to this invention comprises a plurality of logical blocks capable of electrically writing functions and wire elements capable of programmably connecting the logical blocks to each other. Each of the logical blocks includes a gate element as an output buffer having a control terminal. The gate element assumes a high impedance state when inputting a control signal to the control terminal. An output of the logical block is thereby made unable; or the respective logical blocks are directly wired-connectable to effect logical sum outputting. Alternatively, the gate element assumes two output states of an open drain output and a totem-pole output. Hence, in the semiconductor integrated circuit of this invention, it is possible to improve a gate using efficiency of the small-sized programmable logical blocks and attain a high-density and high-integrated programmable logic device.

摘要翻译： 根据本发明的能够电写功能的半导体集成电路包括能够电气地写入功能的多个逻辑块和能够可编程地将逻辑块彼此连接的线元件。 每个逻辑块包括作为具有控制终端的输出缓冲器的门元件。 当向控制端子输入控制信号时，门元件呈现高阻抗状态。 因此，逻辑块的输出不能; 或者各个逻辑块可以直接可连接以实现逻辑和输出。 或者，栅极元件呈现开漏输出和图腾柱输出的两个输出状态。 因此，在本发明的半导体集成电路中，可以提高小型可编程逻辑块的栅极利用效率，并获得高密度和高集成度的可编程逻辑器件。

公开(公告)号：US4942318A

公开(公告)日：1990-07-17

申请号：US251467

申请日：1988-09-30

申请人： Keiichi Kawana

发明人： Keiichi Kawana

IPC分类号： G01R29/027 ,  H03K5/1252 ,  H03K19/173

CPC分类号： G01R29/0273 ,  H03K19/1736 ,  H03K5/1252

摘要： In a programmable input/output circuit connected to an input terminal or an output terminal of an integrated circuit, a desirable combination from signals including a signal of the input terminal, an input or output signal of a storage element, an input or output signal of a combinational logic circuit, an input or output signal of another selector and the like is selected by use of at least one programmable selector, processed and output into the output terminal, so that an input or output circuit for performing a desirable signal process can be provided. Further, at least one dynamic selector circuit is provided, so that an output signal from another input/output circuit can be input into the storage element and an output signal from the storage element can be supplied to another input/output circuit.

公开(公告)号：US5568416A

公开(公告)日：1996-10-22

申请号：US408718

申请日：1995-03-22

申请人： Keiichi Kawana ,  Masato Yoneda ,  Masahiro Konishi

发明人： Keiichi Kawana ,  Masato Yoneda ,  Masahiro Konishi

IPC分类号： G11C15/00

CPC分类号： G11C15/00

摘要： An associative memory device is cascade-connected to form an associative memory. The associative memory device includes a retrieval result register for storing a retrieval result of the lo associative memory device and the retrieval result of the associative memory devices of an upstream side of the associative memory device. An identification code register stores an identification code that indicates whether the associative memory device is a last stage associative memory device of the cascade-connected associative memory devices. If the associative memory device is the last stage associative memory device, the retrieval result stored in the retrieval result register is output. The associative memory outputs the retrieval result only when a signal instructing an output of the retrieval result is received.

摘要翻译： 联结存储器级联连接以形成关联存储器。 关联存储器件包括用于存储联想存储器件的检索结果的检索结果寄存器和关联存储器件的上游侧的关联存储器件的检索结果。 识别代码寄存器存储指示关联存储器件是否是级联连接的存储器件的最后级联想存储器件的识别代码。 如果关联存储器件是最后一级关联存储器件，则输出存储在检索结果寄存器中的检索结果。 只有当接收到指示输出检索结果的信号时，关联存储器输出检索结果。

公开(公告)号：US5126969A

公开(公告)日：1992-06-30

申请号：US563193

申请日：1990-08-06

申请人： Keiichi Kawana

发明人： Keiichi Kawana

IPC分类号： H01L21/82 ,  G11C11/00 ,  G11C16/04 ,  H01L27/10 ,  H03K19/177

CPC分类号： G11C29/50 ,  G11C14/00 ,  G11C29/12 ,  G11C29/1201 ,  G11C29/48 ,  G11C7/24 ,  G11C16/04 ,  G11C2029/1202 ,  G11C2029/5002

摘要： There are provided, in addition to an ordinary operation word line for controlling a non-volatile memory upon regularly writing or reading information, a testing word line, a selection transistor, and a storage capacitor, whereby an input signal is transferred onto the testing word line upon inspection to switch on the selection transistor and hence the information is transferred into the capacitor through a bit line for writing into and reading from the capacitor. More specifically, the selection transistor and the capacitor are operated as in a DRAM to diagnose the function of an integrated circuit chip without operation of the non-volatile memory.

公开(公告)号：US4987319A

公开(公告)日：1991-01-22

申请号：US403443

申请日：1989-09-06

申请人： Keiichi Kawana

发明人： Keiichi Kawana

IPC分类号： H03K19/0175 ,  H03K19/177

CPC分类号： H03K19/17744 ,  H03K19/01759 ,  H03K19/17704 ,  H03K19/17716 ,  H03K19/17792

摘要： In a programmable input/output circuit which is used in a programmable integrated circuit, for interfacing between an external circuit and an internal logic circuit, both disposed exteriorly and interiorly of said integrated circuit, an input/output terminal connected to a bus of the internal logic circuit and a tri-state input buffer are provided, and hereby assured that an external input signal is transmitted to either of the input/output terminal and an ordinary input terminal by switching the status of the tri-state input buffer. In a programmable logic device, which incorporates said input/output circuit, a tri-state buffer is provided between an input/output circuit block and a wiring element, and hereby a driving capability of the wiring element used as a bus line is increased.