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公开(公告)号：US20170187630A1
公开(公告)日：2017-06-29
申请号：US14998301
申请日：2015-12-24
申请人： Keith D. Underwood , Charles A. Giefer , David Addison , Nathan S. Miller , Karl P. Brummel , Stephanie L. Hirnak , Eric R. Borch
发明人： Keith D. Underwood , Charles A. Giefer , David Addison , Nathan S. Miller , Karl P. Brummel , Stephanie L. Hirnak , Eric R. Borch
IPC分类号： H04L12/803 , H04L12/841 , H04W28/02
CPC分类号： H04L47/125 , H04L47/28 , H04L47/32 , H04L47/36 , H04L47/741 , H04W28/0289
摘要： Congestion management techniques for communication networks are described. In an example embodiment, an apparatus may comprise circuitry, a communication component for execution by the circuitry to receive a send request identifying a message to be received from an initiator device via a packet transfer process and transmit an acceptance to grant the send request, and a scheduling component for execution by the circuitry to determine whether to defer the packet transfer process and in response to a determination to defer the packet transfer process, select a value of a delay parameter to be included in the acceptance. Other embodiments are described and claimed.
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公开(公告)号：US20170187579A1
公开(公告)日：2017-06-29
申请号：US14998083
申请日：2015-12-24
IPC分类号： H04L12/24 , H04L12/26 , H04L12/931 , H04L12/935 , H04L12/825
CPC分类号： H04L43/16 , H04L43/0882 , H04L45/125 , H04L45/24
摘要： Systems, apparatuses and methods may provide for a smart power manager that dynamically activates or deactivates the individual lanes of each link of a router based on the allocated power limit and the connected applications. The smart power manager may optimize the router throughput for a given power limit dictated by a global power manager, and use a fine grained credit mechanism to track active lanes. The router power manager may also adjust the number of active lanes for each link individually so that highly utilized links will have more active lanes than links that are idle.
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3.发明申请METHOD AND APPARATUS FOR ACHIEVING NON-INCLUSIVE CACHE PERFORMANCE WITH INCLUSIVE CACHES 有权用于实现包含缓存的非特定缓存性能的方法和设备公开(公告)号：US20120159073A1
公开(公告)日：2012-06-21
申请号：US12973051
申请日：2010-12-20
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/128
摘要： An apparatus and method for improving cache performance in a computer system having a multi-level cache hierarchy. For example, one embodiment of a method comprises: selecting a first line in a cache at level N for potential eviction; querying a cache at level M in the hierarchy to determine whether the first cache line is resident in the cache at level M, wherein M
摘要翻译： 一种用于在具有多级高速缓存层级的计算机系统中提高高速缓存性能的装置和方法。 例如，方法的一个实施例包括：在级别N的高速缓存中选择潜在驱逐的第一行; 查询层级中的级别M的高速缓存，以确定第一高速缓存行是否驻留在级别M的高速缓存中，其中M
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公开(公告)号：US20180089127A1
公开(公告)日：2018-03-29
申请号：US15279830
申请日：2016-09-29
IPC分类号： G06F13/40
CPC分类号： G06F13/4022 , G06F13/4068
摘要： Technologies for a system of communicatively coupled network switches in a hierarchical interconnect network topology include two or more groups that each include two or more first and second level switches in which each of the first level switches are communicatively coupled to each of the plurality of second level switches to form a complete bipartite graph. Additionally, each of the groups is interconnected to each of the other groups via a corresponding global link connecting a second level switch of one group to a corresponding second level switch of another group. Further, each of the first level switches are communicatively coupled to one or more computing nodes. Other embodiments are described herein.
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公开(公告)号：US20180006946A1
公开(公告)日：2018-01-04
申请号：US15200449
申请日：2016-07-01
申请人： Mario Flajslik , Eric R. Borch , Michael A. Parker
发明人： Mario Flajslik , Eric R. Borch , Michael A. Parker
IPC分类号： H04L12/801 , H04L12/935 , H04L12/26
CPC分类号： H04L47/12 , H04L43/062 , H04L43/08 , H04L43/16 , H04L49/25 , H04L49/3027 , H04L49/50
摘要： Technologies for adaptive routing based on network traffic pattern characterization include a network switch configured to receive a network packet via one of a plurality of input ports and identify a set of the plurality of output ports associated with a path usable to forward the received network packet to a destination computing device along. The network switch is further configured to adjust a total congestion value for each of the set of output ports based on a type of the path to which each of the set of output ports corresponds and a value of a minimal path counter to which each of the set of output ports corresponds and enqueue the received network packet into an output buffer queue of one of the set of output ports based on the total congestion value. Other embodiments are described herein.
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公开(公告)号：US20180006945A1
公开(公告)日：2018-01-04
申请号：US15200453
申请日：2016-07-01
IPC分类号： H04L12/801 , H04L12/26 , H04L12/835 , H04L12/935
CPC分类号： H04L47/11 , H04L43/08 , H04L43/0888 , H04L47/30 , H04L49/3027 , H04L49/50
摘要： Technologies for adaptive routing using throughput estimation that includes a network switch. The network switch is configured to determine an adjusted average saturation count for each output buffer queue as a function of a present value of a saturation counter of a corresponding output buffer queue and a weighted average saturation count and a running average saturation count for each of the plurality of output buffer queues as a function of the corresponding captured present value and the adjusted average saturation count. The network switch is further configured to determine a congestion rate value for each output buffer queue and a total congestion value as a function of the congestion rate values and a standard occupancy congestion corresponding to a respective one of the plurality of output buffer queues. Other embodiments are described herein.
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7.发明授权Method and apparatus for achieving non-inclusive cache performance with inclusive caches 有权用于通过包含缓存实现非包容性缓存性能的方法和装置公开(公告)号：US08769209B2
公开(公告)日：2014-07-01
申请号：US12973051
申请日：2010-12-20
IPC分类号： G06F12/12
CPC分类号： G06F12/0813 , G06F12/128
摘要： An apparatus and method for improving cache performance in a computer system having a multi-level cache hierarchy. For example, one embodiment of a method comprises: selecting a first line in a cache at level N for potential eviction; querying a cache at level M in the hierarchy to determine whether the first cache line is resident in the cache at level M, wherein M
摘要翻译： 一种用于在具有多级高速缓存层级的计算机系统中提高高速缓存性能的装置和方法。 例如，方法的一个实施例包括：在级别N的高速缓存中选择潜在驱逐的第一行; 查询层级中的级别M的高速缓存，以确定第一高速缓存行是否驻留在级别M的高速缓存中，其中M
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