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23 条记录 (耗时 0.033 秒)

    Method and system for delta double sampling
    1.
    发明授权
    Method and system for delta double sampling 有权

    公开(公告)号：US08796036B2

    公开(公告)日：2014-08-05

    申请号：US13173851

    申请日：2011-06-30

    申请人： Keith Fife ,  Jungwook Yang

    发明人： Keith Fife ,  Jungwook Yang

    IPC分类号： G01N15/06 ,  G01N27/414

    CPC分类号： G01N27/4148 ,  H03K5/003 ,  Y10S436/806 ,  Y10S436/807 ,  Y10T436/11

    摘要： An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.

    Chemical detection circuit including a serializer circuit
    2.
    发明授权
    Chemical detection circuit including a serializer circuit 有权
    化学检测电路包括串行化电路

    公开(公告)号：US08487790B2

    公开(公告)日：2013-07-16

    申请号：US13174562

    申请日：2011-06-30

    申请人： Keith Fife ,  Jungwook Yang

    发明人： Keith Fife ,  Jungwook Yang

    IPC分类号： H03M9/00

    CPC分类号： G01N27/4148 ,  C12Q1/6869 ,  G01J1/46 ,  G01N27/4143 ,  G01N27/4145 ,  G01N33/00 ,  G01R29/26 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14643 ,  H01L29/66 ,  H01L2924/0002 ,  H04N5/374 ,  Y10T436/25875 ,  H01L2924/00

    摘要： The described embodiments may provide a chemical detection circuit. The chemical detection circuit may comprise a pixel array, a pair of analog-to-digital converter (ADC) circuit blocks, a pair of input/output (I/O) circuit blocks coupled to the pair of ADC circuit blocks respectively, and a plurality of serial link terminals coupled to the pair of IO circuit blocks. The pixel array may comprise a plurality of chemically-sensitive pixels formed in columns and rows. Each chemically-sensitive pixel may comprise: a chemically-sensitive transistor, and a row selection device.

    摘要翻译： 所描述的实施例可以提供化学检测电路。 化学检测电路可以包括像素阵列，一对模数转换器（ADC）电路块，分别耦合到该对ADC电路块的一对输入/输出（I / O）电路块，以及一 耦合到所述一对IO电路块的多个串行链路终端。 像素阵列可以包括以列和行形成的多个化学敏感像素。 每个化学敏感像素可以包括：化学敏感晶体管和行选择器件。

    CMOS active pixel with hard and soft reset
    3.
    发明申请
    CMOS active pixel with hard and soft reset 有权
    CMOS有源像素，硬复位和软复位

    公开(公告)号：US20050083422A1

    公开(公告)日：2005-04-21

    申请号：US10752112

    申请日：2004-01-06

    申请人： Hae-Seung Lee ,  Keith Fife ,  Lane Brooks ,  Jungwook Yang

    发明人： Hae-Seung Lee ,  Keith Fife ,  Lane Brooks ,  Jungwook Yang

    IPC分类号： H04N5/353 ,  H04N5/355 ,  H04N5/359 ,  H04N5/363 ,  H04N5/374 ,  H04N5/335

    CPC分类号： H04N5/3597 ,  H04N5/363 ,  H04N5/3698 ,  H04N5/374 ,  H04N5/3745

    摘要： A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element. The reset transistor hard resets the voltage associated with the light-detecting element and soft resets the voltage associated with the light-detecting element after the generation of the hard reset of the voltage associated with the light-detecting element. A pixel voltage of a column or row line is also measured by hard resetting the column or row line voltage to a first predetermined voltage; soft resetting the column or row line voltage to a first pixel voltage; hard resetting the column or row line voltage to a second predetermined voltage; soft resetting the column or row line voltage to a second pixel voltage; and determining a difference between the first and second pixel voltages, the difference being the measured pixel voltage.

    摘要翻译： 用于成像阵列中的像素位置的电路​​包括将入射光转换为光电流的光检测元件和可操作地连接到光检测元件的复位晶体管，以复位与光检测元件相关联的电压。 复位晶体管硬复位与光检测元件相关联的电压，并且在与光检测元件相关联的电压的硬复位产生之后，软复位与光检测元件相关联的电压。 通过将列或行线电压硬复位到第一预定电压也测量列或行线的像素电压; 将列或行线电压软复位为第一像素电压; 将列或行线电压硬复位到第二预定电压; 将列或行线电压软复位到第二像素电压; 以及确定所述第一和第二像素电压之间的差，所述差是所测量的像素电压。

    CCD-based multi-transistor active pixel sensor array
    4.
    发明授权
    CCD-based multi-transistor active pixel sensor array 有权
    基于CCD的多晶体管有源像素传感器阵列

    公开(公告)号：US08772698B2

    公开(公告)日：2014-07-08

    申请号：US13174245

    申请日：2011-06-30

    申请人： Keith Fife ,  Mark Milgrew

    发明人： Keith Fife ,  Mark Milgrew

    IPC分类号： H01J40/14 ,  G01N27/00 ,  G01N27/403

    CPC分类号： G01N27/4148 ,  C12Q1/6869 ,  G01J1/46 ,  G01N27/4143 ,  G01N27/4145 ,  G01N33/00 ,  G01R29/26 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14643 ,  H01L29/66 ,  H01L2924/0002 ,  H04N5/374 ,  Y10T436/25875 ,  H01L2924/00

    摘要： A floating electrode is used to detect ions in close proximity to the electrode. The electrode is charge coupled to other electrodes and to other transistors to form a pixel that can be placed into an array for addressable readout. It is possible to obtain gain by accumulating charge into another electrode or onto a floating diffusion (FD) node or directly onto the column line. It is desirable to achieve both a reduction in pixel size as well as increase in signal level. To reduce pixel size, ancillary transistors may be eliminated and a charge storage node with certain activation and deactivation sequences may be used.

    摘要翻译： 使用浮动电极来检测靠近电极的离子。 电极电荷耦合到其他电极和其它晶体管，以形成可以放置在阵列中以用于可寻址读出的像素。 可以通过将电荷累积到另一电极或浮动扩散（FD）节点上或直接在列线上来获得增益。 期望实现像素尺寸的减小以及信号电平的增加。 为了减小像素尺寸，可以消除辅助晶体管，并且可以使用具有某些激活和去激活序列的电荷存储节点。

    Matched pair transistor circuits
    5.
    发明授权
    Matched pair transistor circuits 有权
    匹配对晶体管电路

    公开(公告)号：US08685324B2

    公开(公告)日：2014-04-01

    申请号：US13173946

    申请日：2011-06-30

    申请人： Keith Fife

    发明人： Keith Fife

    IPC分类号： G01N15/06

    CPC分类号： G01N27/4148 ,  H03K5/003 ,  Y10S436/806 ,  Y10S436/807 ,  Y10T436/11

    摘要： An array of sensors arranged in matched pairs of transistors with an output formed on a first transistor and a sensor formed on the second transistor of the matched pair. The matched pairs are arranged such that the second transistor in the matched pair is read through the output of the first transistor in the matched pair. The first transistor in the matched pair is forced into the saturation (active) region to prevent interference from the second transistor on the output of the first transistor. A sample is taken of the output. The first transistor is then placed into the linear region allowing the sensor formed on the second transistor to be read through the output of the first transistor. A sample is taken from the output of the sensor reading of the second transistor. A difference is formed of the two samples.

    摘要翻译： 布置成匹配的晶体管对的传感器阵列，其具有形成在第一晶体管上的输出和形成在匹配对的第二晶体管上的传感器。 匹配对被布置成使得匹配对中的第二晶体管通过匹配对中的第一晶体管的输出读取。 匹配对中的第一晶体管被迫进入饱和（有源）区域，以防止第一晶体管的输出上的第二晶体管的干扰。 取出输出的样本。 然后将第一晶体管放置在线性区域中，允许通过第一晶体管的输出读取形成在第二晶体管上的传感器。 样品从第二晶体管的传感器读数的输出中取出。 两个样本形成差异。

    ONE-TRANSISTOR PIXEL ARRAY
    8.
    发明申请
    ONE-TRANSISTOR PIXEL ARRAY 有权
    单晶体像素阵列

    公开(公告)号：US20120168826A1

    公开(公告)日：2012-07-05

    申请号：US13421692

    申请日：2012-03-15

    申请人： Keith Fife

    发明人： Keith Fife

    IPC分类号： H01L27/088

    CPC分类号： G01N27/4148 ,  C12Q1/6869 ,  G01J1/46 ,  G01N27/4143 ,  G01N27/4145 ,  G01N33/00 ,  G01R29/26 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14643 ,  H01L29/66 ,  H01L2924/0002 ,  H04N5/374 ,  Y10T436/25875 ,  H01L2924/00

    摘要： To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column.

    摘要翻译： 为了将像素尺寸减小到最小尺寸和最简单的操作形式，可以通过仅使用一个离子敏感场效应晶体管（ISFET）来形成像素。 该单晶体管或1T像素可以通过将漏极电流转换为列中的电压来提供增益。 可以创建可配置的像素，以便共同的源读取以及源跟随器读出。 多个1T像素可以形成阵列，每列具有多行，多列和列读出电路。

    ONE-TRANSISTOR PIXEL ARRAY WITH CASCODED COLUMN CIRCUIT
    9.
    发明申请
    ONE-TRANSISTOR PIXEL ARRAY WITH CASCODED COLUMN CIRCUIT 有权
    单晶圆像素阵列与圆柱形电路

    公开(公告)号：US20120001236A1

    公开(公告)日：2012-01-05

    申请号：US13174215

    申请日：2011-06-30

    申请人： Keith Fife

    发明人： Keith Fife

    IPC分类号： H01L29/66

    CPC分类号： G01N27/4148 ,  C12Q1/6869 ,  G01J1/46 ,  G01N27/4143 ,  G01N27/4145 ,  G01N33/00 ,  G01R29/26 ,  H01L27/14609 ,  H01L27/14632 ,  H01L27/14643 ,  H01L29/66 ,  H01L2924/0002 ,  H04N5/374 ,  Y10T436/25875 ,  H01L2924/00

    摘要： To reduce the pixel size to the smallest dimensions and simplest form of operation, a pixel may be formed by using only one ion sensitive field-effect transistor (ISFET). This one-transistor, or 1T, pixel can provide gain by converting the drain current to voltage in the column. Configurable pixels can be created to allow both common source read out as well as source follower read out. A plurality of the 1T pixels may form an array, having a number of rows and a number of columns and a column readout circuit in each column. A cascoded device enabled during readout may be used to provide increased programmable gain.

    摘要翻译： 为了将像素尺寸减小到最小尺寸和最简单的操作形式，可以通过仅使用一个离子敏感场效应晶体管（ISFET）来形成像素。 该单晶体管或1T像素可以通过将漏极电流转换为列中的电压来提供增益。 可以创建可配置的像素，以便共同的源读取以及源跟随器读出。 多个1T像素可以形成阵列，每列具有多行，多列和列读出电路。 在读出期间使能的级联器件可用于提供增加的可编程增益。